From f833de765c0b5af50f5abc72e90986700111d3f4 Mon Sep 17 00:00:00 2001 From: Rekai Musuka Date: Fri, 21 Oct 2022 05:12:55 -0300 Subject: [PATCH] chore: don't init bus in Arm7tdmi init --- src/core/cpu.zig | 15 +++++---------- src/core/ppu.zig | 4 ++-- src/main.zig | 16 ++++++++++------ 3 files changed, 17 insertions(+), 18 deletions(-) diff --git a/src/core/cpu.zig b/src/core/cpu.zig index c39c397..c7a44f7 100644 --- a/src/core/cpu.zig +++ b/src/core/cpu.zig @@ -7,7 +7,6 @@ const Bitfield = @import("bitfield").Bitfield; const Scheduler = @import("scheduler.zig").Scheduler; const FilePaths = @import("util.zig").FilePaths; -const Allocator = std.mem.Allocator; const File = std.fs.File; // ARM Instructions @@ -234,7 +233,7 @@ pub const Arm7tdmi = struct { r: [16]u32, sched: *Scheduler, - bus: Bus, + bus: *Bus, cpsr: PSR, spsr: PSR, @@ -252,11 +251,11 @@ pub const Arm7tdmi = struct { log_buf: [0x100]u8, binary_log: bool, - pub fn init(alloc: Allocator, sched: *Scheduler, paths: FilePaths) !Self { + pub fn init(sched: *Scheduler, bus: *Bus) Self { return Self{ .r = [_]u32{0x00} ** 16, .sched = sched, - .bus = try Bus.init(alloc, sched, paths), + .bus = bus, .cpsr = .{ .raw = 0x0000_001F }, .spsr = .{ .raw = 0x0000_0000 }, .banked_fiq = [_]u32{0x00} ** 10, @@ -268,10 +267,6 @@ pub const Arm7tdmi = struct { }; } - pub fn deinit(self: Self) void { - self.bus.deinit(); - } - pub fn useLogger(self: *Self, file: *const File, is_binary: bool) void { self.log_file = file; self.binary_log = is_binary; @@ -433,13 +428,13 @@ pub const Arm7tdmi = struct { const opcode = self.fetch(u16); if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode); - thumb.lut[thumbIdx(opcode)](self, &self.bus, opcode); + thumb.lut[thumbIdx(opcode)](self, self.bus, opcode); } else { const opcode = self.fetch(u32); if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode); if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) { - arm.lut[armIdx(opcode)](self, &self.bus, opcode); + arm.lut[armIdx(opcode)](self, self.bus, opcode); } } } diff --git a/src/core/ppu.zig b/src/core/ppu.zig index 4afa137..42cf7f0 100644 --- a/src/core/ppu.zig +++ b/src/core/ppu.zig @@ -573,7 +573,7 @@ pub const Ppu = struct { // See if HBlank DMA is present and not enabled if (!self.dispstat.vblank.read()) - pollBlankingDma(&cpu.bus, .HBlank); + pollBlankingDma(cpu.bus, .HBlank); self.dispstat.hblank.set(); self.sched.push(.HBlank, 68 * 4 -| late); @@ -615,7 +615,7 @@ pub const Ppu = struct { self.aff_bg[1].latchRefPoints(); // See if Vblank DMA is present and not enabled - pollBlankingDma(&cpu.bus, .VBlank); + pollBlankingDma(cpu.bus, .VBlank); } if (scanline == 227) self.dispstat.vblank.unset(); diff --git a/src/main.zig b/src/main.zig index fdf1db6..acf82e2 100644 --- a/src/main.zig +++ b/src/main.zig @@ -5,6 +5,7 @@ const known_folders = @import("known_folders"); const clap = @import("clap"); const Gui = @import("Gui.zig"); +const Bus = @import("core/Bus.zig"); const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi; const Scheduler = @import("core/scheduler.zig").Scheduler; const FilePaths = @import("core/util.zig").FilePaths; @@ -42,13 +43,16 @@ pub fn main() anyerror!void { var scheduler = Scheduler.init(allocator); defer scheduler.deinit(); - var arm7tdmi = try Arm7tdmi.init(allocator, &scheduler, paths); - arm7tdmi.bus.attach(&arm7tdmi); - if (paths.bios == null) arm7tdmi.fastBoot(); - defer arm7tdmi.deinit(); + var bus = try Bus.init(allocator, &scheduler, paths); + defer bus.deinit(); - var gui = Gui.init(arm7tdmi.bus.pak.title, width, height); - gui.initAudio(&arm7tdmi.bus.apu); + var arm7tdmi = Arm7tdmi.init(&scheduler, &bus); + + bus.attach(&arm7tdmi); // TODO: Shrink Surface (only CPSR and r15?) + if (paths.bios == null) arm7tdmi.fastBoot(); + + var gui = Gui.init(bus.pak.title, width, height); + gui.initAudio(&bus.apu); defer gui.deinit(); try gui.run(&arm7tdmi, &scheduler);