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feat: implement obscure behaviour for ARM data processing instrs 

When a test instruction is called when rd == 15, then the CPSR is
reloaded from the SPSR, the pipline is not flushed
This commit is contained in:
Rekai Nyangadzayi Musuka 2022-07-02 10:07:52 -03:00
parent 7a1633e99a
commit d7aa7d0a9e
2 changed files with 6 additions and 1 deletions
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5
src/cpu.zig
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@ -154,6 +154,11 @@ pub const Arm7tdmi = struct {
return self.bus.io.haltcnt == .Halt;
}
pub fn setCpsrNoFlush(self: *Self, value: u32) void {
if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
self.cpsr.raw = value;
}
pub fn setCpsr(self: *Self, value: u32) void {
if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));

2
src/cpu/arm/data_processing.zig
View File

@ -282,5 +282,5 @@ fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) vo
fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
@setCold(true);
cpu.setCpsr(cpu.spsr.raw);
cpu.setCpsrNoFlush(cpu.spsr.raw);
}