From d7aa7d0a9e1ded88fac85882b77f75d5e619ddca Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Sat, 2 Jul 2022 10:07:52 -0300
Subject: [PATCH] feat: implement obscure behaviour for ARM data processing
 instrs

When a test instruction is called when rd == 15, then the CPSR is
reloaded from the SPSR, the pipline is not flushed
---
 src/cpu.zig                     | 5 +++++
 src/cpu/arm/data_processing.zig | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/cpu.zig b/src/cpu.zig
index 0dcab8b..bb0c64a 100644
--- a/src/cpu.zig
+++ b/src/cpu.zig
@@ -154,6 +154,11 @@ pub const Arm7tdmi = struct {
         return self.bus.io.haltcnt == .Halt;
     }
 
+    pub fn setCpsrNoFlush(self: *Self, value: u32) void {
+        if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
+        self.cpsr.raw = value;
+    }
+
     pub fn setCpsr(self: *Self, value: u32) void {
         if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
 
diff --git a/src/cpu/arm/data_processing.zig b/src/cpu/arm/data_processing.zig
index acbfeb0..597ab68 100644
--- a/src/cpu/arm/data_processing.zig
+++ b/src/cpu/arm/data_processing.zig
@@ -282,5 +282,5 @@ fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) vo
 
 fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
     @setCold(true);
-    cpu.setCpsr(cpu.spsr.raw);
+    cpu.setCpsrNoFlush(cpu.spsr.raw);
 }