chore(cpu): refactor ARM functions to make room for THUMB
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51
src/cpu/arm/psr_transfer.zig
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51
src/cpu/arm/psr_transfer.zig
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@@ -0,0 +1,51 @@
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const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").InstrFn;
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pub fn psrTransfer(comptime I: bool, comptime isSpsr: bool) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
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switch (@truncate(u3, opcode >> 19)) {
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0b001 => {
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// MRS
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const rn = opcode >> 12 & 0xF;
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if (isSpsr) {
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std.debug.panic("[CPU] TODO: MRS on SPSR_<current_mode> is unimplemented", .{});
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} else {
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cpu.r[rn] = cpu.cpsr.raw;
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}
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},
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0b101 => {
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// MSR
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const rm = opcode & 0xF;
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switch (@truncate(u3, opcode >> 16)) {
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0b000 => {
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const right = if (I) std.math.rotr(u32, opcode & 0xFF, opcode >> 7 & 0xF) else cpu.r[rm];
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if (isSpsr) {
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std.debug.panic("[CPU] TODO: MSR (flags only) on SPSR_<current_mode> is unimplemented", .{});
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} else {
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const mask: u32 = 0xF000_0000;
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cpu.cpsr.raw = (cpu.cpsr.raw & ~mask) | (right & mask);
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}
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},
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0b001 => {
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if (isSpsr) {
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std.debug.panic("[CPU] TODO: MSR on SPSR_<current_mode> is unimplemented", .{});
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} else {
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cpu.cpsr = .{ .raw = cpu.r[rm] };
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}
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},
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else => unreachable,
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}
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},
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else => unreachable,
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}
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}
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}.inner;
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}
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