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fix(cpu): op == 0b00 decodes to add in format 5

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-02-02 18:58:06 -04:00
parent 784bc81a4a
commit 9affe01da8
1 changed files with 2 additions and 1 deletions
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3
src/cpu/thumb/format5.zig
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@ -5,6 +5,7 @@ const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
const cmp = @import("../arm/data_processing.zig").cmp;
const add = @import("../arm/data_processing.zig").add;
pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
return struct {
@ -13,6 +14,7 @@ pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
const dst = @as(u4, h1) << 3 | (opcode & 0x7);
switch (op) {
0b00 => cpu.r[dst] = add(false, cpu, cpu.r[dst], cpu.r[src]), // ADD
0b01 => cmp(cpu, cpu.r[dst], cpu.r[src]), // CMP
0b10 => cpu.r[dst] = cpu.r[src], // MOV
0b11 => {
@ -20,7 +22,6 @@ pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
cpu.cpsr.t.write(cpu.r[src] & 1 == 1);
cpu.r[15] = cpu.r[src] & 0xFFFF_FFFE;
},
else => cpu.panic("[CPU|THUMB|Fmt5] {} is an invalid op", .{op}),
}
}
}.inner;