From 9affe01da84ad0ef5ddd517d72b09cfc8da7ea03 Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Wed, 2 Feb 2022 18:58:06 -0400
Subject: [PATCH] fix(cpu): op == 0b00 decodes to add in format 5

---
 src/cpu/thumb/format5.zig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/cpu/thumb/format5.zig b/src/cpu/thumb/format5.zig
index 33fb5b7..5c50bb2 100644
--- a/src/cpu/thumb/format5.zig
+++ b/src/cpu/thumb/format5.zig
@@ -5,6 +5,7 @@ const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
 
 const cmp = @import("../arm/data_processing.zig").cmp;
+const add = @import("../arm/data_processing.zig").add;
 
 pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
     return struct {
@@ -13,6 +14,7 @@ pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
             const dst = @as(u4, h1) << 3 | (opcode & 0x7);
 
             switch (op) {
+                0b00 => cpu.r[dst] = add(false, cpu, cpu.r[dst], cpu.r[src]), // ADD
                 0b01 => cmp(cpu, cpu.r[dst], cpu.r[src]), // CMP
                 0b10 => cpu.r[dst] = cpu.r[src], // MOV
                 0b11 => {
@@ -20,7 +22,6 @@ pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
                     cpu.cpsr.t.write(cpu.r[src] & 1 == 1);
                     cpu.r[15] = cpu.r[src] & 0xFFFF_FFFE;
                 },
-                else => cpu.panic("[CPU|THUMB|Fmt5] {} is an invalid op", .{op}),
             }
         }
     }.inner;