fix(cpu): op == 0b00 decodes to add in format 5
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784bc81a4a
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@ -5,6 +5,7 @@ const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
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const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
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const cmp = @import("../arm/data_processing.zig").cmp;
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const cmp = @import("../arm/data_processing.zig").cmp;
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const add = @import("../arm/data_processing.zig").add;
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pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
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pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
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return struct {
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return struct {
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@ -13,6 +14,7 @@ pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
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const dst = @as(u4, h1) << 3 | (opcode & 0x7);
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const dst = @as(u4, h1) << 3 | (opcode & 0x7);
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switch (op) {
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switch (op) {
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0b00 => cpu.r[dst] = add(false, cpu, cpu.r[dst], cpu.r[src]), // ADD
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0b01 => cmp(cpu, cpu.r[dst], cpu.r[src]), // CMP
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0b01 => cmp(cpu, cpu.r[dst], cpu.r[src]), // CMP
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0b10 => cpu.r[dst] = cpu.r[src], // MOV
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0b10 => cpu.r[dst] = cpu.r[src], // MOV
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0b11 => {
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0b11 => {
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@ -20,7 +22,6 @@ pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
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cpu.cpsr.t.write(cpu.r[src] & 1 == 1);
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cpu.cpsr.t.write(cpu.r[src] & 1 == 1);
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cpu.r[15] = cpu.r[src] & 0xFFFF_FFFE;
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cpu.r[15] = cpu.r[src] & 0xFFFF_FFFE;
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},
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},
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else => cpu.panic("[CPU|THUMB|Fmt5] {} is an invalid op", .{op}),
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}
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}
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}
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}
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}.inner;
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}.inner;
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