chore: progress towards passing ldr/str thumb in armwrestler

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-02-02 21:14:46 -04:00
parent 8b574efe85
commit 99492a6782
4 changed files with 69 additions and 4 deletions

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@ -28,6 +28,7 @@ const format3 = @import("cpu/thumb/format3.zig").format3;
const format4 = @import("cpu/thumb/format4.zig").format4; const format4 = @import("cpu/thumb/format4.zig").format4;
const format5 = @import("cpu/thumb/format5.zig").format5; const format5 = @import("cpu/thumb/format5.zig").format5;
const format6 = @import("cpu/thumb/format6.zig").format6; const format6 = @import("cpu/thumb/format6.zig").format6;
const format78 = @import("cpu/thumb/format78.zig").format78;
const format9 = @import("cpu/thumb/format9.zig").format9; const format9 = @import("cpu/thumb/format9.zig").format9;
const format10 = @import("cpu/thumb/format10.zig").format10; const format10 = @import("cpu/thumb/format10.zig").format10;
const format12 = @import("cpu/thumb/format12.zig").format12; const format12 = @import("cpu/thumb/format12.zig").format12;
@ -450,8 +451,10 @@ fn thumbPopulate() [0x400]ThumbInstrFn {
lut[i] = format6(rd); lut[i] = format6(rd);
} else if (i >> 6 & 0xF == 0b0101) { } else if (i >> 6 & 0xF == 0b0101) {
// TODO: Format 7 and Format 8 const op = i >> 5 & 0x3;
lut[i] = thumbUndefined; const T = i >> 3 & 1 == 1;
lut[i] = format78(op, T);
} else if (i >> 7 & 0x7 == 0b000) { } else if (i >> 7 & 0x7 == 0b000) {
const op = i >> 5 & 0x3; const op = i >> 5 & 0x3;
const offset = i & 0x1F; const offset = i & 0x1F;

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@ -14,7 +14,8 @@ pub fn format10(comptime L: bool, comptime offset: u5) InstrFn {
if (L) { if (L) {
// LDRH // LDRH
cpu.r[rd] = bus.read16(address & 0xFFFF_FFFE); const value = bus.read16(address & 0xFFFF_FFFE);
cpu.r[rd] = std.math.rotr(u32, @as(u32, value), 8 * (address & 1));
} else { } else {
// STRH // STRH
bus.write16(address & 0xFFFF_FFFE, @truncate(u16, cpu.r[rd])); bus.write16(address & 0xFFFF_FFFE, @truncate(u16, cpu.r[rd]));

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@ -0,0 +1,60 @@
const std = @import("std");
const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
const u32SignExtend = @import("../../util.zig").u32SignExtend;
pub fn format78(comptime op: u2, comptime T: bool) InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
const ro = opcode >> 6 & 0x7;
const rb = opcode >> 3 & 0x7;
const rd = opcode & 0x7;
const address = cpu.r[rb] + cpu.r[ro];
if (T) {
switch (op) {
0b00 => {
// STRH
bus.write16(address & 0xFFFF_FFFE, @truncate(u16, cpu.r[rd]));
},
0b01 => {
// LDRH
const value = bus.read16(address & 0xFFFF_FFFE);
cpu.r[rd] = std.math.rotr(u32, @as(u32, value), 8 * (address & 1));
},
0b10 => {
// LDSB
cpu.r[rd] = u32SignExtend(8, @as(u32, bus.read8(address)));
},
0b11 => {
// LDSH
cpu.r[rd] = u32SignExtend(16, @as(u32, bus.read16(address & 0xFFFF_FFFE)));
},
}
} else {
switch (op) {
0b00 => {
// STR
bus.write32(address & 0xFFFF_FFFC, cpu.r[rd]);
},
0b01 => {
// STRB
bus.write8(address, @truncate(u8, cpu.r[rd]));
},
0b10 => {
// LDR
const value = bus.read32(address & 0xFFFF_FFFC);
cpu.r[rd] = std.math.rotr(u32, value, 8 * (address & 0x3));
},
0b11 => {
// LDRB
cpu.r[rd] = bus.read8(address);
},
}
}
}
}.inner;
}

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@ -18,7 +18,8 @@ pub fn format9(comptime B: bool, comptime L: bool, comptime offset: u5) InstrFn
} else { } else {
// LDR // LDR
const address = cpu.r[rb] + (@as(u32, offset) << 2); const address = cpu.r[rb] + (@as(u32, offset) << 2);
cpu.r[rd] = bus.read32(address & 0xFFFF_FFFC); const value = bus.read32(address & 0xFFFF_FFFC);
cpu.r[rd] = std.math.rotr(u32, value, 8 * (address & 0x3));
} }
} else { } else {
if (B) { if (B) {