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fix(cpu): fix obscure LDRSH behaviour

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-10-22 22:12:41 -03:00
parent 945dbec013
commit 928ce674d9
2 changed files with 4 additions and 10 deletions
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7
src/core/cpu/arm/half_signed_data_transfer.zig
View File

@ -35,11 +35,8 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
}, },
0b11 => { 0b11 => {
// LDRSH // LDRSH
result = if (address & 1 == 1) blk: { const value = bus.read(u16, address);
break :blk sext(u32, u8, bus.read(u8, address)); result = if (address & 1 == 1) sext(u32, u8, @truncate(u8, value >> 8)) else sext(u32, u16, value);
} else blk: {
break :blk sext(u32, u16, bus.read(u16, address));
};
}, },
0b00 => unreachable, // SWP 0b00 => unreachable, // SWP
} }

7
src/core/cpu/thumb/data_transfer.zig
View File

@ -46,11 +46,8 @@ pub fn fmt78(comptime op: u2, comptime T: bool) InstrFn {
}, },
0b11 => { 0b11 => {
// LDRSH // LDRSH
cpu.r[rd] = if (address & 1 == 1) blk: { const value = bus.read(u16, address);
break :blk sext(u32, u8, bus.read(u8, address)); cpu.r[rd] = if (address & 1 == 1) sext(u32, u8, @truncate(u8, value >> 8)) else sext(u32, u16, value);
} else blk: {
break :blk sext(u32, u16, bus.read(u16, address));
};
}, },
} }
} else { } else {