From 928ce674d9ad776bb0c6e96d4934bb6e41d1808e Mon Sep 17 00:00:00 2001 From: Rekai Musuka Date: Sat, 22 Oct 2022 22:12:41 -0300 Subject: [PATCH] fix(cpu): fix obscure LDRSH behaviour --- src/core/cpu/arm/half_signed_data_transfer.zig | 7 ++----- src/core/cpu/thumb/data_transfer.zig | 7 ++----- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/src/core/cpu/arm/half_signed_data_transfer.zig b/src/core/cpu/arm/half_signed_data_transfer.zig index 2b12ec4..d6c334a 100644 --- a/src/core/cpu/arm/half_signed_data_transfer.zig +++ b/src/core/cpu/arm/half_signed_data_transfer.zig @@ -35,11 +35,8 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: }, 0b11 => { // LDRSH - result = if (address & 1 == 1) blk: { - break :blk sext(u32, u8, bus.read(u8, address)); - } else blk: { - break :blk sext(u32, u16, bus.read(u16, address)); - }; + const value = bus.read(u16, address); + result = if (address & 1 == 1) sext(u32, u8, @truncate(u8, value >> 8)) else sext(u32, u16, value); }, 0b00 => unreachable, // SWP } diff --git a/src/core/cpu/thumb/data_transfer.zig b/src/core/cpu/thumb/data_transfer.zig index 5e76291..3c55942 100644 --- a/src/core/cpu/thumb/data_transfer.zig +++ b/src/core/cpu/thumb/data_transfer.zig @@ -46,11 +46,8 @@ pub fn fmt78(comptime op: u2, comptime T: bool) InstrFn { }, 0b11 => { // LDRSH - cpu.r[rd] = if (address & 1 == 1) blk: { - break :blk sext(u32, u8, bus.read(u8, address)); - } else blk: { - break :blk sext(u32, u16, bus.read(u16, address)); - }; + const value = bus.read(u16, address); + cpu.r[rd] = if (address & 1 == 1) sext(u32, u8, @truncate(u8, value >> 8)) else sext(u32, u16, value); }, } } else {