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chore: reimplement bus read/writes

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-04-08 16:48:43 -03:00
parent 37a360ec07
commit 80e714e2eb
11 changed files with 130 additions and 166 deletions
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181
src/Bus.zig
View File

@ -54,136 +54,91 @@ pub fn deinit(self: Self) void {
self.ppu.deinit(); self.ppu.deinit();
} }
pub fn read32(self: *const Self, address: u32) u32 { pub fn read(self: *const Self, comptime T: type, address: u32) T {
const align_addr = address & 0xFFFF_FFFC; // Force Aligned const page = @truncate(u8, address >> 24);
const align_addr = alignAddress(T, address);
return switch (address) { return switch (page) {
// General Internal Memory // General Internal Memory
0x0000_0000...0x0000_3FFF => self.bios.read(u32, align_addr), 0x00 => self.bios.read(T, align_addr),
0x0200_0000...0x02FF_FFFF => self.ewram.read(u32, align_addr), 0x02 => self.ewram.read(T, align_addr),
0x0300_0000...0x03FF_FFFF => self.iwram.read(u32, align_addr), 0x03 => self.iwram.read(T, align_addr),
0x0400_0000...0x0400_03FE => io.read32(self, align_addr), 0x04 => switch (T) {
u32 => io.read32(self, align_addr),
// Internal Display Memory u16 => io.read16(self, align_addr),
0x0500_0000...0x05FF_FFFF => self.ppu.palette.read(u32, align_addr), u8 => io.read8(self, align_addr),
0x0600_0000...0x06FF_FFFF => self.ppu.vram.read(u32, align_addr), else => @compileError("I/O: Unsupported read width"),
0x0700_0000...0x07FF_FFFF => self.ppu.oam.read(u32, align_addr),
// External Memory (Game Pak)
0x0800_0000...0x09FF_FFFF => self.pak.read(u32, align_addr),
0x0A00_0000...0x0BFF_FFFF => self.pak.read(u32, align_addr),
0x0C00_0000...0x0DFF_FFFF => self.pak.read(u32, align_addr),
0x0E00_0000...0x0FFF_FFFF => @as(u32, self.pak.backup.read(address)) * 0x01010101,
else => undRead("Tried to read from 0x{X:0>8}", .{address}),
};
}
pub fn write32(self: *Self, address: u32, word: u32) void {
const align_addr = address & 0xFFFF_FFFC; // Force Aligned
switch (address) {
// General Internal Memory
0x0200_0000...0x02FF_FFFF => self.ewram.write(u32, align_addr, word),
0x0300_0000...0x03FF_FFFF => self.iwram.write(u32, align_addr, word),
0x0400_0000...0x0400_03FE => io.write32(self, align_addr, word),
// Internal Display Memory
0x0500_0000...0x05FF_FFFF => self.ppu.palette.write(u32, align_addr, word),
0x0600_0000...0x06FF_FFFF => self.ppu.vram.write(u32, align_addr, word),
0x0700_0000...0x07FF_FFFF => self.ppu.oam.write(u32, align_addr, word),
0x0E00_0000...0x0FFF_FFFF => self.pak.backup.write(address, @truncate(u8, rotr(u32, word, 8 * (address & 3)))),
else => undWrite("Tried to write 0x{X:0>8} to 0x{X:0>8}", .{ word, address }),
}
}
pub fn read16(self: *const Self, address: u32) u16 {
const align_addr = address & 0xFFFF_FFFE; // Force Aligned
return switch (address) {
// General Internal Memory
0x0000_0000...0x0000_3FFF => self.bios.read(u16, align_addr),
0x0200_0000...0x02FF_FFFF => self.ewram.read(u16, align_addr),
0x0300_0000...0x03FF_FFFF => self.iwram.read(u16, align_addr),
0x0400_0000...0x0400_03FE => io.read16(self, align_addr),
// Internal Display Memory
0x0500_0000...0x05FF_FFFF => self.ppu.palette.read(u16, align_addr),
0x0600_0000...0x06FF_FFFF => self.ppu.vram.read(u16, align_addr),
0x0700_0000...0x07FF_FFFF => self.ppu.oam.read(u16, align_addr),
// External Memory (Game Pak)
0x0800_0000...0x09FF_FFFF => self.pak.read(u16, align_addr),
0x0A00_0000...0x0BFF_FFFF => self.pak.read(u16, align_addr),
0x0C00_0000...0x0DFF_FFFF => self.pak.read(u16, align_addr),
0x0E00_0000...0x0FFF_FFFF => @as(u16, self.pak.backup.read(address)) * 0x0101,
else => undRead("Tried to read from 0x{X:0>8}", .{address}),
};
}
pub fn write16(self: *Self, address: u32, halfword: u16) void {
const align_addr = address & 0xFFFF_FFFE;
switch (address) {
// General Internal Memory
0x0200_0000...0x02FF_FFFF => self.ewram.write(u16, align_addr, halfword),
0x0300_0000...0x03FF_FFFF => self.iwram.write(u16, align_addr, halfword),
0x0400_0000...0x0400_03FE => io.write16(self, align_addr, halfword),
// Internal Display Memory
0x0500_0000...0x05FF_FFFF => self.ppu.palette.write(u16, align_addr, halfword),
0x0600_0000...0x06FF_FFFF => self.ppu.vram.write(u16, align_addr, halfword),
0x0700_0000...0x07FF_FFFF => self.ppu.oam.write(u16, align_addr, halfword),
0x0800_00C4, 0x0800_00C6, 0x0800_00C8 => log.warn("Tried to write 0x{X:0>4} to GPIO", .{halfword}),
// External Memory (Game Pak)
0x0E00_0000...0x0FFF_FFFF => {
self.pak.backup.write(address, @truncate(u8, rotr(u16, halfword, 8 * (address & 1))));
}, },
else => undWrite("Tried to write 0x{X:0>4} to 0x{X:0>8}", .{ halfword, address }),
}
}
pub fn read8(self: *const Self, address: u32) u8 {
return switch (address) {
// General Internal Memory
0x0000_0000...0x0000_3FFF => self.bios.read(u8, address),
0x0200_0000...0x02FF_FFFF => self.ewram.read(u8, address),
0x0300_0000...0x03FF_FFFF => self.iwram.read(u8, address),
0x0400_0000...0x0400_03FE => io.read8(self, address),
// Internal Display Memory // Internal Display Memory
0x0500_0000...0x05FF_FFFF => self.ppu.palette.read(u8, address), 0x05 => self.ppu.palette.read(T, align_addr),
0x0600_0000...0x06FF_FFFF => self.ppu.vram.read(u8, address), 0x06 => self.ppu.vram.read(T, align_addr),
0x0700_0000...0x07FF_FFFF => self.ppu.oam.read(u8, address), 0x07 => self.ppu.oam.read(T, align_addr),
// External Memory (Game Pak) // External Memory (Game Pak)
0x0800_0000...0x09FF_FFFF => self.pak.read(u8, address), 0x08...0x0D => self.pak.read(T, align_addr),
0x0A00_0000...0x0BFF_FFFF => self.pak.read(u8, address), 0x0E...0x0F => blk: {
0x0C00_0000...0x0DFF_FFFF => self.pak.read(u8, address), const value = self.pak.backup.read(address);
0x0E00_0000...0x0FFF_FFFF => self.pak.backup.read(address),
else => undRead("Tried to read from 0x{X:0>2}", .{address}), const multiplier = switch (T) {
u32 => 0x01010101,
u16 => 0x0101,
u8 => 1,
else => @compileError("Backup: Unsupported read width"),
};
break :blk @as(T, value) * multiplier;
},
else => undRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
}; };
} }
pub fn write8(self: *Self, address: u32, byte: u8) void { pub fn write(self: *Self, comptime T: type, address: u32, value: T) void {
switch (address) { const page = @truncate(u8, address >> 24);
const align_addr = alignAddress(T, address);
switch (page) {
// General Internal Memory // General Internal Memory
0x0200_0000...0x02FF_FFFF => self.ewram.write(u8, address, byte), 0x00 => self.bios.write(T, align_addr, value),
0x0300_0000...0x03FF_FFFF => self.iwram.write(u8, address, byte), 0x02 => self.ewram.write(T, align_addr, value),
0x0400_0000...0x0400_03FE => io.write8(self, address, byte), 0x03 => self.iwram.write(T, align_addr, value),
0x0400_0410 => log.info("Ignored write of 0x{X:0>2} to 0x{X:0>8}", .{ byte, address }), 0x04 => switch (T) {
u32 => io.write32(self, align_addr, value),
u16 => io.write16(self, align_addr, value),
u8 => io.write8(self, align_addr, value),
else => @compileError("I/O: Unsupported write width"),
},
// Internal Display Memory
0x05 => self.ppu.palette.write(T, align_addr, value),
0x06 => self.ppu.vram.write(T, align_addr, value),
0x07 => self.ppu.oam.write(T, align_addr, value),
// External Memory (Game Pak) // External Memory (Game Pak)
0x0E00_0000...0x0FFF_FFFF => self.pak.backup.write(address, byte), 0x08...0x0D => {},
else => undWrite("Tried to write 0x{X:0>2} to 0x{X:0>8}", .{ byte, address }), 0x0E...0x0F => {
const rotate_by = switch (T) {
u32 => address & 3,
u16 => address & 1,
u8 => 0,
else => @compileError("Backup: Unsupported write width"),
};
self.pak.backup.write(address, @truncate(u8, rotr(T, value, 8 * rotate_by)));
},
else => undWrite("Tried to write {} 0x{X:} to 0x{X:0>8}", .{ T, value, address }),
} }
} }
fn alignAddress(comptime T: type, address: u32) u32 {
return switch (T) {
u32 => address & 0xFFFF_FFFC,
u16 => address & 0xFFFF_FFFE,
u8 => address,
else => @compileError("Bus: Invalid read/write type"),
};
}
fn undRead(comptime format: []const u8, args: anytype) u8 { fn undRead(comptime format: []const u8, args: anytype) u8 {
if (panic_on_und_bus) std.debug.panic(format, args) else log.warn(format, args); if (panic_on_und_bus) std.debug.panic(format, args) else log.warn(format, args);
return 0; return 0;

6
src/bus/Bios.zig
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@ -1,6 +1,7 @@
const std = @import("std"); const std = @import("std");
const Allocator = std.mem.Allocator; const Allocator = std.mem.Allocator;
const log = std.log.scoped(.Bios);
const Self = @This(); const Self = @This();
buf: ?[]u8, buf: ?[]u8,
@ -38,3 +39,8 @@ pub fn read(self: *const Self, comptime T: type, addr: usize) T {
std.debug.panic("[BIOS] ZBA tried to read {} from 0x{X:0>8} but not BIOS was present", .{ T, addr }); std.debug.panic("[BIOS] ZBA tried to read {} from 0x{X:0>8} but not BIOS was present", .{ T, addr });
} }
pub fn write(_: *Self, comptime T: type, addr: usize, value: T) void {
@setCold(true);
log.err("Tried to write {} 0x{X:} to 0x{X:0>8} ", .{ T, value, addr });
}

8
src/bus/dma.zig
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@ -123,12 +123,12 @@ fn DmaController(comptime id: u2) type {
var offset: u32 = 0; var offset: u32 = 0;
if (self.cnt.transfer_type.read()) { if (self.cnt.transfer_type.read()) {
offset = @sizeOf(u32); // 32-bit Transfer offset = @sizeOf(u32); // 32-bit Transfer
const word = bus.read32(self._sad); const word = bus.read(u32, self._sad);
bus.write32(self._dad, word); bus.write(u32, self._dad, word);
} else { } else {
offset = @sizeOf(u16); // 16-bit Transfer offset = @sizeOf(u16); // 16-bit Transfer
const halfword = bus.read16(self._sad); const halfword = bus.read(u16, self._sad);
bus.write16(self._dad, halfword); bus.write(u16, self._dad, halfword);
} }
switch (sad_adj) { switch (sad_adj) {

10
src/cpu.zig
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@ -306,12 +306,12 @@ pub const Arm7tdmi = struct {
fn thumbFetch(self: *Self) u16 { fn thumbFetch(self: *Self) u16 {
defer self.r[15] += 2; defer self.r[15] += 2;
return self.bus.read16(self.r[15]); return self.bus.read(u16, self.r[15]);
} }
fn fetch(self: *Self) u32 { fn fetch(self: *Self) u32 {
defer self.r[15] += 4; defer self.r[15] += 4;
return self.bus.read32(self.r[15]); return self.bus.read(u32, self.r[15]);
} }
pub fn fakePC(self: *const Self) u32 { pub fn fakePC(self: *const Self) u32 {
@ -341,11 +341,11 @@ pub const Arm7tdmi = struct {
prettyPrintPsr(&self.spsr); prettyPrintPsr(&self.spsr);
if (self.cpsr.t.read()) { if (self.cpsr.t.read()) {
const opcode = self.bus.read16(self.r[15] - 4); const opcode = self.bus.read(u16, self.r[15] - 4);
const id = thumbIdx(opcode); const id = thumbIdx(opcode);
std.debug.print("opcode: ID: 0x{b:0>10} 0x{X:0>4}\n", .{ id, opcode }); std.debug.print("opcode: ID: 0x{b:0>10} 0x{X:0>4}\n", .{ id, opcode });
} else { } else {
const opcode = self.bus.read32(self.r[15] - 4); const opcode = self.bus.read(u32, self.r[15] - 4);
const id = armIdx(opcode); const id = armIdx(opcode);
std.debug.print("opcode: ID: 0x{X:0>3} 0x{X:0>8}\n", .{ id, opcode }); std.debug.print("opcode: ID: 0x{X:0>3} 0x{X:0>8}\n", .{ id, opcode });
} }
@ -432,7 +432,7 @@ pub const Arm7tdmi = struct {
if (self.cpsr.t.read()) { if (self.cpsr.t.read()) {
if (opcode >> 11 == 0x1E) { if (opcode >> 11 == 0x1E) {
// Instruction 1 of a BL Opcode, print in ARM mode // Instruction 1 of a BL Opcode, print in ARM mode
const tmp_opcode = self.bus.read32(self.r[15] - 2); const tmp_opcode = self.bus.read(u32, self.r[15] - 2);
const be_opcode = tmp_opcode << 16 | tmp_opcode >> 16; const be_opcode = tmp_opcode << 16 | tmp_opcode >> 16;
log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, be_opcode }); log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, be_opcode });
} else { } else {

12
src/cpu/arm/block_data_transfer.zig
View File

@ -54,9 +54,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
} }
if (L) { if (L) {
cpu.r[15] = bus.read32(und_addr); cpu.r[15] = bus.read(u32, und_addr);
} else { } else {
bus.write32(und_addr, cpu.r[15] + 8); bus.write(u32, und_addr, cpu.r[15] + 8);
} }
cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40; cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
@ -83,9 +83,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
if (L) { if (L) {
if (S and !r15_present) { if (S and !r15_present) {
// Always Transfer User mode Registers // Always Transfer User mode Registers
cpu.setUserModeRegister(i, bus.read32(address)); cpu.setUserModeRegister(i, bus.read(u32, address));
} else { } else {
const value = bus.read32(address); const value = bus.read(u32, address);
cpu.r[i] = if (i == 0xF) value & 0xFFFF_FFFC else value; cpu.r[i] = if (i == 0xF) value & 0xFFFF_FFFC else value;
if (S and i == 0xF) cpu.setCpsr(cpu.spsr.raw); if (S and i == 0xF) cpu.setCpsr(cpu.spsr.raw);
} }
@ -94,9 +94,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
// Always Transfer User mode Registers // Always Transfer User mode Registers
// This happens regardless if r15 is in the list // This happens regardless if r15 is in the list
const value = cpu.getUserModeRegister(i); const value = cpu.getUserModeRegister(i);
bus.write32(address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12 bus.write(u32, address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
} else { } else {
bus.write32(address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0)); bus.write(u32, address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
} }
} }
} }

10
src/cpu/arm/half_signed_data_transfer.zig
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@ -38,19 +38,19 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
switch (@truncate(u2, opcode >> 5)) { switch (@truncate(u2, opcode >> 5)) {
0b01 => { 0b01 => {
// LDRH // LDRH
const value = bus.read16(address); const value = bus.read(u16, address);
result = rotr(u32, value, 8 * (address & 1)); result = rotr(u32, value, 8 * (address & 1));
}, },
0b10 => { 0b10 => {
// LDRSB // LDRSB
result = sext(8, bus.read8(address)); result = sext(8, bus.read(u8, address));
}, },
0b11 => { 0b11 => {
// LDRSH // LDRSH
const value = if (address & 1 == 1) blk: { const value = if (address & 1 == 1) blk: {
break :blk sext(8, bus.read8(address)); break :blk sext(8, bus.read(u8, address));
} else blk: { } else blk: {
break :blk sext(16, bus.read16(address)); break :blk sext(16, bus.read(u16, address));
}; };
result = rotr(u32, value, 8 * (address & 1)); result = rotr(u32, value, 8 * (address & 1));
@ -60,7 +60,7 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
} else { } else {
if (opcode >> 5 & 0x01 == 0x01) { if (opcode >> 5 & 0x01 == 0x01) {
// STRH // STRH
bus.write16(address, @truncate(u16, cpu.r[rd])); bus.write(u16, address, @truncate(u16, cpu.r[rd]));
} else unreachable; // SWP } else unreachable; // SWP
} }

8
src/cpu/arm/single_data_swap.zig
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@ -17,13 +17,13 @@ pub fn singleDataSwap(comptime B: bool) InstrFn {
if (B) { if (B) {
// SWPB // SWPB
const value = bus.read8(address); const value = bus.read(u8, address);
bus.write8(address, @truncate(u8, cpu.r[rm])); bus.write(u8, address, @truncate(u8, cpu.r[rm]));
cpu.r[rd] = value; cpu.r[rd] = value;
} else { } else {
// SWP // SWP
const value = rotr(u32, bus.read32(address), 8 * (address & 0x3)); const value = rotr(u32, bus.read(u32, address), 8 * (address & 0x3));
bus.write32(address, cpu.r[rm]); bus.write(u32, address, cpu.r[rm]);
cpu.r[rd] = value; cpu.r[rd] = value;
} }
} }

8
src/cpu/arm/single_data_transfer.zig
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@ -31,21 +31,21 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
if (L) { if (L) {
if (B) { if (B) {
// LDRB // LDRB
result = bus.read8(address); result = bus.read(u8, address);
} else { } else {
// LDR // LDR
const value = bus.read32(address); const value = bus.read(u32, address);
result = rotr(u32, value, 8 * (address & 0x3)); result = rotr(u32, value, 8 * (address & 0x3));
} }
} else { } else {
if (B) { if (B) {
// STRB // STRB
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd]; const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
bus.write8(address, @truncate(u8, value)); bus.write(u8, address, @truncate(u8, value));
} else { } else {
// STR // STR
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd]; const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
bus.write32(address, value); bus.write(u32, address, value);
} }
} }

14
src/cpu/thumb/block_data_transfer.zig
View File

@ -21,9 +21,9 @@ pub fn format14(comptime L: bool, comptime R: bool) InstrFn {
while (i < 8) : (i += 1) { while (i < 8) : (i += 1) {
if (opcode >> i & 1 == 1) { if (opcode >> i & 1 == 1) {
if (L) { if (L) {
cpu.r[i] = bus.read32(address); cpu.r[i] = bus.read(u32, address);
} else { } else {
bus.write32(address, cpu.r[i]); bus.write(u32, address, cpu.r[i]);
} }
address += 4; address += 4;
@ -32,10 +32,10 @@ pub fn format14(comptime L: bool, comptime R: bool) InstrFn {
if (R) { if (R) {
if (L) { if (L) {
const value = bus.read32(address); const value = bus.read(u32, address);
cpu.r[15] = value & 0xFFFF_FFFE; cpu.r[15] = value & 0xFFFF_FFFE;
} else { } else {
bus.write32(address, cpu.r[14]); bus.write(u32, address, cpu.r[14]);
} }
address += 4; address += 4;
} }
@ -52,7 +52,7 @@ pub fn format15(comptime L: bool, comptime rb: u3) InstrFn {
const end_address = cpu.r[rb] + 4 * countRlist(opcode); const end_address = cpu.r[rb] + 4 * countRlist(opcode);
if (opcode & 0xFF == 0) { if (opcode & 0xFF == 0) {
if (L) cpu.r[15] = bus.read32(address) else bus.write32(address, cpu.r[15] + 4); if (L) cpu.r[15] = bus.read(u32, address) else bus.write(u32, address, cpu.r[15] + 4);
cpu.r[rb] += 0x40; cpu.r[rb] += 0x40;
return; return;
} }
@ -63,9 +63,9 @@ pub fn format15(comptime L: bool, comptime rb: u3) InstrFn {
while (i < 8) : (i += 1) { while (i < 8) : (i += 1) {
if (opcode >> i & 1 == 1) { if (opcode >> i & 1 == 1) {
if (L) { if (L) {
cpu.r[i] = bus.read32(address); cpu.r[i] = bus.read(u32, address);
} else { } else {
bus.write32(address, cpu.r[i]); bus.write(u32, address, cpu.r[i]);
} }
if (!L and first_write) { if (!L and first_write) {

36
src/cpu/thumb/data_transfer.zig
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@ -11,7 +11,7 @@ pub fn format6(comptime rd: u3) InstrFn {
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void { fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
// LDR // LDR
const offset = (opcode & 0xFF) << 2; const offset = (opcode & 0xFF) << 2;
cpu.r[rd] = bus.read32((cpu.r[15] + 2 & 0xFFFF_FFFD) + offset); cpu.r[rd] = bus.read(u32, (cpu.r[15] + 2 & 0xFFFF_FFFD) + offset);
} }
}.inner; }.inner;
} }
@ -32,23 +32,23 @@ pub fn format78(comptime op: u2, comptime T: bool) InstrFn {
switch (op) { switch (op) {
0b00 => { 0b00 => {
// STRH // STRH
bus.write16(address, @truncate(u16, cpu.r[rd])); bus.write(u16, address, @truncate(u16, cpu.r[rd]));
}, },
0b01 => { 0b01 => {
// LDSB // LDSB
cpu.r[rd] = sext(8, bus.read8(address)); cpu.r[rd] = sext(8, bus.read(u8, address));
}, },
0b10 => { 0b10 => {
// LDRH // LDRH
const value = bus.read16(address); const value = bus.read(u16, address);
cpu.r[rd] = rotr(u32, value, 8 * (address & 1)); cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
}, },
0b11 => { 0b11 => {
// LDRSH // LDRSH
const value = if (address & 1 == 1) blk: { const value = if (address & 1 == 1) blk: {
break :blk sext(8, bus.read8(address)); break :blk sext(8, bus.read(u8, address));
} else blk: { } else blk: {
break :blk sext(16, bus.read16(address)); break :blk sext(16, bus.read(u16, address));
}; };
cpu.r[rd] = rotr(u32, value, 8 * (address & 1)); cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
@ -59,20 +59,20 @@ pub fn format78(comptime op: u2, comptime T: bool) InstrFn {
switch (op) { switch (op) {
0b00 => { 0b00 => {
// STR // STR
bus.write32(address, cpu.r[rd]); bus.write(u32, address, cpu.r[rd]);
}, },
0b01 => { 0b01 => {
// STRB // STRB
bus.write8(address, @truncate(u8, cpu.r[rd])); bus.write(u8, address, @truncate(u8, cpu.r[rd]));
}, },
0b10 => { 0b10 => {
// LDR // LDR
const value = bus.read32(address); const value = bus.read(u32, address);
cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3)); cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
}, },
0b11 => { 0b11 => {
// LDRB // LDRB
cpu.r[rd] = bus.read8(address); cpu.r[rd] = bus.read(u8, address);
}, },
} }
} }
@ -90,22 +90,22 @@ pub fn format9(comptime B: bool, comptime L: bool, comptime offset: u5) InstrFn
if (B) { if (B) {
// LDRB // LDRB
const address = cpu.r[rb] + offset; const address = cpu.r[rb] + offset;
cpu.r[rd] = bus.read8(address); cpu.r[rd] = bus.read(u8, address);
} else { } else {
// LDR // LDR
const address = cpu.r[rb] + (@as(u32, offset) << 2); const address = cpu.r[rb] + (@as(u32, offset) << 2);
const value = bus.read32(address); const value = bus.read(u32, address);
cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3)); cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
} }
} else { } else {
if (B) { if (B) {
// STRB // STRB
const address = cpu.r[rb] + offset; const address = cpu.r[rb] + offset;
bus.write8(address, @truncate(u8, cpu.r[rd])); bus.write(u8, address, @truncate(u8, cpu.r[rd]));
} else { } else {
// STR // STR
const address = cpu.r[rb] + (@as(u32, offset) << 2); const address = cpu.r[rb] + (@as(u32, offset) << 2);
bus.write32(address, cpu.r[rd]); bus.write(u32, address, cpu.r[rd]);
} }
} }
} }
@ -122,11 +122,11 @@ pub fn format10(comptime L: bool, comptime offset: u5) InstrFn {
if (L) { if (L) {
// LDRH // LDRH
const value = bus.read16(address); const value = bus.read(u16, address);
cpu.r[rd] = rotr(u32, value, 8 * (address & 1)); cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
} else { } else {
// STRH // STRH
bus.write16(address, @truncate(u16, cpu.r[rd])); bus.write(u16, address, @truncate(u16, cpu.r[rd]));
} }
} }
}.inner; }.inner;
@ -140,11 +140,11 @@ pub fn format11(comptime L: bool, comptime rd: u3) InstrFn {
if (L) { if (L) {
// LDR // LDR
const value = bus.read32(address); const value = bus.read(u32, address);
cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3)); cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
} else { } else {
// STR // STR
bus.write32(address, cpu.r[rd]); bus.write(u32, address, cpu.r[rd]);
} }
} }
}.inner; }.inner;

3
src/ppu.zig
View File

@ -457,6 +457,7 @@ const Palette = struct {
self.buf[addr + 1] = @truncate(u8, value >> 8); self.buf[addr + 1] = @truncate(u8, value >> 8);
self.buf[addr + 0] = @truncate(u8, value >> 0); self.buf[addr + 0] = @truncate(u8, value >> 0);
}, },
u8 => log.err("Tried to write {} 0x{X:0>2} to 0x{X:0>8}", .{ T, value, address }),
else => @compileError("PALRAM: Unsupported write width"), else => @compileError("PALRAM: Unsupported write width"),
} }
} }
@ -511,6 +512,7 @@ const Vram = struct {
self.buf[addr + 1] = @truncate(u8, value >> 8); self.buf[addr + 1] = @truncate(u8, value >> 8);
self.buf[addr + 0] = @truncate(u8, value >> 0); self.buf[addr + 0] = @truncate(u8, value >> 0);
}, },
u8 => log.err("Tried to write {} 0x{X:0>2} to 0x{X:0>8}", .{ T, value, address }),
else => @compileError("VRAM: Unsupported write width"), else => @compileError("VRAM: Unsupported write width"),
} }
} }
@ -566,6 +568,7 @@ const Oam = struct {
self.buf[addr + 1] = @truncate(u8, value >> 8); self.buf[addr + 1] = @truncate(u8, value >> 8);
self.buf[addr + 0] = @truncate(u8, value >> 0); self.buf[addr + 0] = @truncate(u8, value >> 0);
}, },
u8 => log.err("Tried to write {} 0x{X:0>2} to 0x{X:0>8}", .{ T, value, address }),
else => @compileError("OAM: Unsupported write width"), else => @compileError("OAM: Unsupported write width"),
} }
} }