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chore: reimplement bus read/writes

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This commit is contained in:
Rekai Nyangadzayi Musuka
2022-04-08 16:48:43 -03:00
parent 37a360ec07
commit 80e714e2eb
11 changed files with 130 additions and 166 deletions
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12
src/cpu/arm/block_data_transfer.zig
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@@ -54,9 +54,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
}
if (L) {
cpu.r[15] = bus.read32(und_addr);
cpu.r[15] = bus.read(u32, und_addr);
} else {
bus.write32(und_addr, cpu.r[15] + 8);
bus.write(u32, und_addr, cpu.r[15] + 8);
}
cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
@@ -83,9 +83,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
if (L) {
if (S and !r15_present) {
// Always Transfer User mode Registers
cpu.setUserModeRegister(i, bus.read32(address));
cpu.setUserModeRegister(i, bus.read(u32, address));
} else {
const value = bus.read32(address);
const value = bus.read(u32, address);
cpu.r[i] = if (i == 0xF) value & 0xFFFF_FFFC else value;
if (S and i == 0xF) cpu.setCpsr(cpu.spsr.raw);
}
@@ -94,9 +94,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
// Always Transfer User mode Registers
// This happens regardless if r15 is in the list
const value = cpu.getUserModeRegister(i);
bus.write32(address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
bus.write(u32, address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
} else {
bus.write32(address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
bus.write(u32, address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
}
}
}

10
src/cpu/arm/half_signed_data_transfer.zig
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@@ -38,19 +38,19 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
switch (@truncate(u2, opcode >> 5)) {
0b01 => {
// LDRH
const value = bus.read16(address);
const value = bus.read(u16, address);
result = rotr(u32, value, 8 * (address & 1));
},
0b10 => {
// LDRSB
result = sext(8, bus.read8(address));
result = sext(8, bus.read(u8, address));
},
0b11 => {
// LDRSH
const value = if (address & 1 == 1) blk: {
break :blk sext(8, bus.read8(address));
break :blk sext(8, bus.read(u8, address));
} else blk: {
break :blk sext(16, bus.read16(address));
break :blk sext(16, bus.read(u16, address));
};
result = rotr(u32, value, 8 * (address & 1));
@@ -60,7 +60,7 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
} else {
if (opcode >> 5 & 0x01 == 0x01) {
// STRH
bus.write16(address, @truncate(u16, cpu.r[rd]));
bus.write(u16, address, @truncate(u16, cpu.r[rd]));
} else unreachable; // SWP
}

8
src/cpu/arm/single_data_swap.zig
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@@ -17,13 +17,13 @@ pub fn singleDataSwap(comptime B: bool) InstrFn {
if (B) {
// SWPB
const value = bus.read8(address);
bus.write8(address, @truncate(u8, cpu.r[rm]));
const value = bus.read(u8, address);
bus.write(u8, address, @truncate(u8, cpu.r[rm]));
cpu.r[rd] = value;
} else {
// SWP
const value = rotr(u32, bus.read32(address), 8 * (address & 0x3));
bus.write32(address, cpu.r[rm]);
const value = rotr(u32, bus.read(u32, address), 8 * (address & 0x3));
bus.write(u32, address, cpu.r[rm]);
cpu.r[rd] = value;
}
}

8
src/cpu/arm/single_data_transfer.zig
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@@ -31,21 +31,21 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
if (L) {
if (B) {
// LDRB
result = bus.read8(address);
result = bus.read(u8, address);
} else {
// LDR
const value = bus.read32(address);
const value = bus.read(u32, address);
result = rotr(u32, value, 8 * (address & 0x3));
}
} else {
if (B) {
// STRB
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
bus.write8(address, @truncate(u8, value));
bus.write(u8, address, @truncate(u8, value));
} else {
// STR
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
bus.write32(address, value);
bus.write(u32, address, value);
}
}