feat(cpu): implement SWP
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@ -35,7 +35,9 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
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switch (@truncate(u2, opcode >> 5)) {
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0b00 => {
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// SWP
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std.debug.panic("[CPU] TODO: Implement SWP", .{});
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const value = bus.read32(cpu.r[rn]);
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const tmp = std.math.rotr(u32, value, 8 * (cpu.r[rn] & 0x3));
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bus.write32(cpu.r[rm], tmp);
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},
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0b01 => {
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// LDRH
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@ -45,12 +47,12 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
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0b10 => {
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// LDRSB
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cpu.r[rd] = util.u32SignExtend(8, @as(u32, bus.read8(address)));
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std.debug.panic("TODO: Affect the CPSR", .{});
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std.debug.panic("[CPU|ARM|LDRSB] TODO: Affect the CPSR", .{});
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},
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0b11 => {
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// LDRSH
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cpu.r[rd] = util.u32SignExtend(16, @as(u32, bus.read16(address)));
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std.debug.panic("TODO: Affect the CPSR", .{});
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std.debug.panic("[CPU|ARM|LDRSH] TODO: Affect the CPSR", .{});
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},
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}
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} else {
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