From 7e6fc44191c2c5bd9dd1965b77786b46888885b5 Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Fri, 21 Oct 2022 05:12:08 -0300
Subject: [PATCH] feat(cpu): implement SWP

---
 src/cpu/arm/half_signed_data_transfer.zig | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/cpu/arm/half_signed_data_transfer.zig b/src/cpu/arm/half_signed_data_transfer.zig
index 264d0c1..d2a725f 100644
--- a/src/cpu/arm/half_signed_data_transfer.zig
+++ b/src/cpu/arm/half_signed_data_transfer.zig
@@ -35,7 +35,9 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
                 switch (@truncate(u2, opcode >> 5)) {
                     0b00 => {
                         // SWP
-                        std.debug.panic("[CPU] TODO: Implement SWP", .{});
+                        const value = bus.read32(cpu.r[rn]);
+                        const tmp = std.math.rotr(u32, value, 8 * (cpu.r[rn] & 0x3));
+                        bus.write32(cpu.r[rm], tmp);
                     },
                     0b01 => {
                         // LDRH
@@ -45,12 +47,12 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
                     0b10 => {
                         // LDRSB
                         cpu.r[rd] = util.u32SignExtend(8, @as(u32, bus.read8(address)));
-                        std.debug.panic("TODO: Affect the CPSR", .{});
+                        std.debug.panic("[CPU|ARM|LDRSB] TODO: Affect the CPSR", .{});
                     },
                     0b11 => {
                         // LDRSH
                         cpu.r[rd] = util.u32SignExtend(16, @as(u32, bus.read16(address)));
-                        std.debug.panic("TODO: Affect the CPSR", .{});
+                        std.debug.panic("[CPU|ARM|LDRSH] TODO: Affect the CPSR", .{});
                     },
                 }
             } else {