style: changes to cpu.zig
This commit is contained in:
parent
7d8fbbb086
commit
558c03b12b
244
src/core/cpu.zig
244
src/core/cpu.zig
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@ -7,6 +7,7 @@ const Scheduler = @import("scheduler.zig").Scheduler;
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const Logger = @import("../util.zig").Logger;
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const File = std.fs.File;
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const log = std.log.scoped(.Arm7Tdmi);
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// ARM Instructions
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pub const arm = struct {
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@ -234,8 +235,6 @@ pub const thumb = struct {
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}
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};
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const log = std.log.scoped(.Arm7Tdmi);
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pub const Arm7tdmi = struct {
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const Self = @This();
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@ -246,18 +245,64 @@ pub const Arm7tdmi = struct {
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cpsr: PSR,
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spsr: PSR,
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/// Storage for R8_fiq -> R12_fiq and their normal counterparts
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/// e.g [r[0 + 8], fiq_r[0 + 8], r[1 + 8], fiq_r[1 + 8]...]
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banked_fiq: [2 * 5]u32,
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/// Storage for r13_<mode>, r14_<mode>
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/// e.g. [r13, r14, r13_svc, r14_svc]
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banked_r: [2 * 6]u32,
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banked_spsr: [5]PSR,
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bank: Bank,
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logger: ?Logger,
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/// Bank of Registers from other CPU Modes
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const Bank = struct {
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/// Storage for r13_<mode>, r14_<mode>
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/// e.g. [r13, r14, r13_svc, r14_svc]
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r: [2 * 6]u32,
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/// Storage for R8_fiq -> R12_fiq and their normal counterparts
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/// e.g [r[0 + 8], fiq_r[0 + 8], r[1 + 8], fiq_r[1 + 8]...]
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fiq: [2 * 5]u32,
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spsr: [5]PSR,
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const Kind = enum(u1) {
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R13 = 0,
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R14,
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};
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pub fn create() Bank {
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return .{
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.r = [_]u32{0x00} ** 12,
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.fiq = [_]u32{0x00} ** 10,
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.spsr = [_]PSR{.{ .raw = 0x0000_0000 }} ** 5,
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};
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}
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inline fn regIdx(mode: Mode, kind: Kind) usize {
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const idx: usize = switch (mode) {
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.User, .System => 0,
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.Supervisor => 1,
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.Abort => 2,
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.Undefined => 3,
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.Irq => 4,
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.Fiq => 5,
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};
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return (idx * 2) + if (kind == .R14) @as(usize, 1) else 0;
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}
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inline fn spsrIdx(mode: Mode) usize {
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return switch (mode) {
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.Supervisor => 0,
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.Abort => 1,
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.Undefined => 2,
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.Irq => 3,
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.Fiq => 4,
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else => std.debug.panic("[CPU/Mode] {} does not have a SPSR Register", .{mode}),
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};
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}
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inline fn fiqIdx(i: usize, mode: Mode) usize {
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return (i * 2) + if (mode == .Fiq) @as(usize, 1) else 0;
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}
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};
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pub fn init(sched: *Scheduler, bus: *Bus, log_file: ?std.fs.File) Self {
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return Self{
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.r = [_]u32{0x00} ** 16,
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@ -266,41 +311,11 @@ pub const Arm7tdmi = struct {
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.bus = bus,
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.cpsr = .{ .raw = 0x0000_001F },
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.spsr = .{ .raw = 0x0000_0000 },
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.banked_fiq = [_]u32{0x00} ** 10,
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.banked_r = [_]u32{0x00} ** 12,
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.banked_spsr = [_]PSR{.{ .raw = 0x0000_0000 }} ** 5,
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.bank = Bank.create(),
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.logger = if (log_file) |file| Logger.init(file) else null,
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};
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}
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inline fn bankedIdx(mode: Mode, kind: BankedKind) usize {
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const idx: usize = switch (mode) {
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.User, .System => 0,
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.Supervisor => 1,
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.Abort => 2,
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.Undefined => 3,
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.Irq => 4,
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.Fiq => 5,
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};
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return (idx * 2) + if (kind == .R14) @as(usize, 1) else 0;
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}
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inline fn bankedSpsrIndex(mode: Mode) usize {
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return switch (mode) {
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.Supervisor => 0,
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.Abort => 1,
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.Undefined => 2,
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.Irq => 3,
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.Fiq => 4,
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else => std.debug.panic("[CPU/Mode] {} does not have a SPSR Register", .{mode}),
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};
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}
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inline fn bankedFiqIdx(i: usize, mode: Mode) usize {
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return (i * 2) + if (mode == .Fiq) @as(usize, 1) else 0;
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}
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pub inline fn hasSPSR(self: *const Self) bool {
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const mode = getModeChecked(self, self.cpsr.mode.read());
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return switch (mode) {
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@ -336,14 +351,14 @@ pub const Arm7tdmi = struct {
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switch (idx) {
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8...12 => {
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if (current == .Fiq) {
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self.banked_fiq[bankedFiqIdx(idx - 8, .User)] = value;
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self.bank.fiq[Bank.fiqIdx(idx - 8, .User)] = value;
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} else self.r[idx] = value;
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},
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13, 14 => switch (current) {
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.User, .System => self.r[idx] = value,
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else => {
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const kind = std.meta.intToEnum(BankedKind, idx - 13) catch unreachable;
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self.banked_r[bankedIdx(.User, kind)] = value;
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const kind = std.meta.intToEnum(Bank.Kind, idx - 13) catch unreachable;
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self.bank.r[Bank.regIdx(.User, kind)] = value;
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},
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},
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else => self.r[idx] = value, // R0 -> R7 and R15
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@ -354,12 +369,12 @@ pub const Arm7tdmi = struct {
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const current = getModeChecked(self, self.cpsr.mode.read());
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return switch (idx) {
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8...12 => if (current == .Fiq) self.banked_fiq[bankedFiqIdx(idx - 8, .User)] else self.r[idx],
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8...12 => if (current == .Fiq) self.bank.fiq[Bank.fiqIdx(idx - 8, .User)] else self.r[idx],
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13, 14 => switch (current) {
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.User, .System => self.r[idx],
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else => blk: {
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const kind = std.meta.intToEnum(BankedKind, idx - 13) catch unreachable;
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break :blk self.banked_r[bankedIdx(.User, kind)];
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const kind = std.meta.intToEnum(Bank.Kind, idx - 13) catch unreachable;
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break :blk self.bank.r[Bank.regIdx(.User, kind)];
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},
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},
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else => self.r[idx], // R0 -> R7 and R15
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@ -372,38 +387,38 @@ pub const Arm7tdmi = struct {
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// Bank R8 -> r12
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var i: usize = 0;
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while (i < 5) : (i += 1) {
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self.banked_fiq[bankedFiqIdx(i, now)] = self.r[8 + i];
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self.bank.fiq[Bank.fiqIdx(i, now)] = self.r[8 + i];
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}
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// Bank r13, r14, SPSR
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switch (now) {
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.User, .System => {
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self.banked_r[bankedIdx(now, .R13)] = self.r[13];
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self.banked_r[bankedIdx(now, .R14)] = self.r[14];
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self.bank.r[Bank.regIdx(now, .R13)] = self.r[13];
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self.bank.r[Bank.regIdx(now, .R14)] = self.r[14];
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},
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else => {
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self.banked_r[bankedIdx(now, .R13)] = self.r[13];
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self.banked_r[bankedIdx(now, .R14)] = self.r[14];
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self.banked_spsr[bankedSpsrIndex(now)] = self.spsr;
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self.bank.r[Bank.regIdx(now, .R13)] = self.r[13];
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self.bank.r[Bank.regIdx(now, .R14)] = self.r[14];
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self.bank.spsr[Bank.spsrIdx(now)] = self.spsr;
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},
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}
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// Grab R8 -> R12
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i = 0;
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while (i < 5) : (i += 1) {
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self.r[8 + i] = self.banked_fiq[bankedFiqIdx(i, next)];
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self.r[8 + i] = self.bank.fiq[Bank.fiqIdx(i, next)];
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}
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// Grab r13, r14, SPSR
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switch (next) {
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.User, .System => {
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self.r[13] = self.banked_r[bankedIdx(next, .R13)];
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self.r[14] = self.banked_r[bankedIdx(next, .R14)];
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self.r[13] = self.bank.r[Bank.regIdx(next, .R13)];
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self.r[14] = self.bank.r[Bank.regIdx(next, .R14)];
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},
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else => {
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self.r[13] = self.banked_r[bankedIdx(next, .R13)];
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self.r[14] = self.banked_r[bankedIdx(next, .R14)];
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self.spsr = self.banked_spsr[bankedSpsrIndex(next)];
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self.r[13] = self.bank.r[Bank.regIdx(next, .R13)];
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self.r[14] = self.bank.r[Bank.regIdx(next, .R14)];
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self.spsr = self.bank.spsr[Bank.spsrIdx(next)];
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},
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}
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@ -424,8 +439,8 @@ pub const Arm7tdmi = struct {
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self.r[13] = 0x0300_7F00;
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self.r[15] = 0x0800_0000;
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self.banked_r[bankedIdx(.Irq, .R13)] = 0x0300_7FA0;
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self.banked_r[bankedIdx(.Supervisor, .R13)] = 0x0300_7FE0;
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self.bank.r[Bank.regIdx(.Irq, .R13)] = 0x0300_7FA0;
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self.bank.r[Bank.regIdx(.Supervisor, .R13)] = 0x0300_7FE0;
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// self.cpsr.raw = 0x6000001F;
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self.cpsr.raw = 0x0000_001F;
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@ -515,10 +530,10 @@ pub const Arm7tdmi = struct {
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std.debug.print("R{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\n", .{ i, self.r[i], i_1, self.r[i_1], i_2, self.r[i_2], i_3, self.r[i_3] });
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}
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std.debug.print("cpsr: 0x{X:0>8} ", .{self.cpsr.raw});
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prettyPrintPsr(&self.cpsr);
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self.cpsr.toString();
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std.debug.print("spsr: 0x{X:0>8} ", .{self.spsr.raw});
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prettyPrintPsr(&self.spsr);
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self.spsr.toString();
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std.debug.print("pipeline: {??X:0>8}\n", .{self.pipe.stage});
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@ -536,76 +551,6 @@ pub const Arm7tdmi = struct {
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std.debug.panic(format, args);
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}
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fn prettyPrintPsr(psr: *const PSR) void {
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std.debug.print("[", .{});
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if (psr.n.read()) std.debug.print("N", .{}) else std.debug.print("-", .{});
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if (psr.z.read()) std.debug.print("Z", .{}) else std.debug.print("-", .{});
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if (psr.c.read()) std.debug.print("C", .{}) else std.debug.print("-", .{});
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if (psr.v.read()) std.debug.print("V", .{}) else std.debug.print("-", .{});
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if (psr.i.read()) std.debug.print("I", .{}) else std.debug.print("-", .{});
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if (psr.f.read()) std.debug.print("F", .{}) else std.debug.print("-", .{});
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if (psr.t.read()) std.debug.print("T", .{}) else std.debug.print("-", .{});
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std.debug.print("|", .{});
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if (getMode(psr.mode.read())) |mode| std.debug.print("{s}", .{modeString(mode)}) else std.debug.print("---", .{});
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std.debug.print("]\n", .{});
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}
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fn modeString(mode: Mode) []const u8 {
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return switch (mode) {
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.User => "usr",
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.Fiq => "fiq",
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.Irq => "irq",
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.Supervisor => "svc",
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.Abort => "abt",
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.Undefined => "und",
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.System => "sys",
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};
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}
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fn mgbaLog(self: *const Self, file: *const File, opcode: u32) !void {
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const thumb_fmt = "{X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} cpsr: {X:0>8} | {X:0>4}:\n";
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const arm_fmt = "{X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} cpsr: {X:0>8} | {X:0>8}:\n";
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var buf: [0x100]u8 = [_]u8{0x00} ** 0x100; // this is larger than it needs to be
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const r0 = self.r[0];
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const r1 = self.r[1];
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const r2 = self.r[2];
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const r3 = self.r[3];
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const r4 = self.r[4];
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const r5 = self.r[5];
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const r6 = self.r[6];
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const r7 = self.r[7];
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const r8 = self.r[8];
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const r9 = self.r[9];
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const r10 = self.r[10];
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const r11 = self.r[11];
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const r12 = self.r[12];
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const r13 = self.r[13];
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const r14 = self.r[14];
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const r15 = self.r[15] -| if (self.cpsr.t.read()) 2 else @as(u32, 4);
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const c_psr = self.cpsr.raw;
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var log_str: []u8 = undefined;
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if (self.cpsr.t.read()) {
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if (opcode >> 11 == 0x1E) {
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// Instruction 1 of a BL Opcode, print in ARM mode
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const other_half = self.bus.debugRead(u16, self.r[15] - 2);
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const bl_opcode = @as(u32, opcode) << 16 | other_half;
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log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, bl_opcode });
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} else {
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log_str = try std.fmt.bufPrint(&buf, thumb_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode });
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}
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} else {
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log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode });
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}
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_ = try file.writeAll(log_str);
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}
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};
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const condition_lut = [_]u16{
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@ -684,6 +629,22 @@ pub const PSR = extern union {
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z: Bit(u32, 30),
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n: Bit(u32, 31),
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raw: u32,
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fn toString(self: PSR) void {
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std.debug.print("[", .{});
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if (self.n.read()) std.debug.print("N", .{}) else std.debug.print("-", .{});
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if (self.z.read()) std.debug.print("Z", .{}) else std.debug.print("-", .{});
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if (self.c.read()) std.debug.print("C", .{}) else std.debug.print("-", .{});
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if (self.v.read()) std.debug.print("V", .{}) else std.debug.print("-", .{});
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if (self.i.read()) std.debug.print("I", .{}) else std.debug.print("-", .{});
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if (self.f.read()) std.debug.print("F", .{}) else std.debug.print("-", .{});
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if (self.t.read()) std.debug.print("T", .{}) else std.debug.print("-", .{});
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std.debug.print("|", .{});
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if (getMode(self.mode.read())) |m| std.debug.print("{s}", .{m.toString()}) else std.debug.print("---", .{});
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std.debug.print("]\n", .{});
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}
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};
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const Mode = enum(u5) {
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@ -694,11 +655,18 @@ const Mode = enum(u5) {
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Abort = 0b10111,
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Undefined = 0b11011,
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System = 0b11111,
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};
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const BankedKind = enum(u1) {
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R13 = 0,
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R14,
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fn toString(self: Mode) []const u8 {
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return switch (self) {
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.User => "usr",
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.Fiq => "fiq",
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.Irq => "irq",
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.Supervisor => "svc",
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.Abort => "abt",
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.Undefined => "und",
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.System => "sys",
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};
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}
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};
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fn getMode(bits: u5) ?Mode {
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