chore: move OAM, PALRAM and VRAM structs to separate files
This commit is contained in:
parent
d6304a7382
commit
5351c14e12
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@ -266,7 +266,7 @@ fn DmaController(comptime id: u2) type {
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};
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}
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pub fn pollDmaOnBlank(bus: *Bus, comptime kind: DmaKind) void {
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pub fn onBlanking(bus: *Bus, comptime kind: DmaKind) void {
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bus.dma[0].poll(kind);
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bus.dma[1].poll(kind);
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bus.dma[2].poll(kind);
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170
src/core/ppu.zig
170
src/core/ppu.zig
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@ -1,16 +1,18 @@
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const std = @import("std");
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const io = @import("bus/io.zig");
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const Bit = @import("bitfield").Bit;
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const Bitfield = @import("bitfield").Bitfield;
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const dma = @import("bus/dma.zig");
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const Oam = @import("ppu/Oam.zig");
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const Palette = @import("ppu/Palette.zig");
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const Vram = @import("ppu/Vram.zig");
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const EventKind = @import("scheduler.zig").EventKind;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
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const Bit = @import("bitfield").Bit;
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const Bitfield = @import("bitfield").Bitfield;
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const Allocator = std.mem.Allocator;
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const log = std.log.scoped(.PPU);
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const pollDmaOnBlank = @import("bus/dma.zig").pollDmaOnBlank;
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pub const width = 240;
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pub const height = 160;
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@ -485,7 +487,7 @@ pub const Ppu = struct {
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while (i < width) : (i += 1) {
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// If we're outside of the bounds of mode 5, draw the background colour
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const bgr555 =
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if (scanline < m5_height and i < m5_width) self.vram.read(u16, vram_base + i * @sizeOf(u16)) else self.palette.getBackdrop();
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if (scanline < m5_height and i < m5_width) self.vram.read(u16, vram_base + i * @sizeOf(u16)) else self.palette.backdrop();
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std.mem.writeIntNative(u32, self.framebuf.get(.Emulator)[fb_base + i * @sizeOf(u32) ..][0..@sizeOf(u32)], rgba888(bgr555));
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}
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@ -529,7 +531,7 @@ pub const Ppu = struct {
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}
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if (maybe_top) |top| return top;
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return self.palette.getBackdrop();
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return self.palette.backdrop();
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}
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fn copyToBackgroundBuffer(self: *Self, comptime n: u2, bounds: ?WindowBounds, i: usize, bgr555: u16) void {
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@ -658,7 +660,7 @@ pub const Ppu = struct {
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// See if HBlank DMA is present and not enabled
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if (!self.dispstat.vblank.read())
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pollDmaOnBlank(cpu.bus, .HBlank);
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dma.onBlanking(cpu.bus, .HBlank);
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self.dispstat.hblank.set();
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self.sched.push(.HBlank, 68 * 4 -| late);
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@ -700,7 +702,7 @@ pub const Ppu = struct {
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self.aff_bg[1].latchRefPoints();
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// See if Vblank DMA is present and not enabled
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pollDmaOnBlank(cpu.bus, .VBlank);
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dma.onBlanking(cpu.bus, .VBlank);
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}
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if (scanline == 227) self.dispstat.vblank.unset();
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@ -709,158 +711,6 @@ pub const Ppu = struct {
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}
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};
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const Palette = struct {
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const palram_size = 0x400;
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const Self = @This();
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buf: []u8,
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allocator: Allocator,
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fn init(allocator: Allocator) !Self {
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const buf = try allocator.alloc(u8, palram_size);
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std.mem.set(u8, buf, 0);
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return Self{
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.buf = buf,
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.allocator = allocator,
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};
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}
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fn deinit(self: *Self) void {
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self.allocator.free(self.buf);
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self.* = undefined;
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}
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pub fn read(self: *const Self, comptime T: type, address: usize) T {
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const addr = address & 0x3FF;
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return switch (T) {
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u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
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else => @compileError("PALRAM: Unsupported read width"),
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};
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}
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pub fn write(self: *Self, comptime T: type, address: usize, value: T) void {
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const addr = address & 0x3FF;
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switch (T) {
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u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
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u8 => {
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const align_addr = addr & ~@as(u32, 1); // Aligned to Halfword boundary
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std.mem.writeIntSliceLittle(u16, self.buf[align_addr..][0..@sizeOf(u16)], @as(u16, value) * 0x101);
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},
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else => @compileError("PALRAM: Unsupported write width"),
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}
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}
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fn getBackdrop(self: *const Self) u16 {
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return self.read(u16, 0);
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}
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};
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const Vram = struct {
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const vram_size = 0x18000;
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const Self = @This();
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buf: []u8,
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allocator: Allocator,
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fn init(allocator: Allocator) !Self {
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const buf = try allocator.alloc(u8, vram_size);
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std.mem.set(u8, buf, 0);
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return Self{
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.buf = buf,
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.allocator = allocator,
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};
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}
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fn deinit(self: *Self) void {
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self.allocator.free(self.buf);
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self.* = undefined;
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}
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pub fn read(self: *const Self, comptime T: type, address: usize) T {
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const addr = Self.mirror(address);
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return switch (T) {
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u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
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else => @compileError("VRAM: Unsupported read width"),
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};
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}
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pub fn write(self: *Self, comptime T: type, dispcnt: io.DisplayControl, address: usize, value: T) void {
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const mode: u3 = dispcnt.bg_mode.read();
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const idx = Self.mirror(address);
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switch (T) {
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u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[idx..][0..@sizeOf(T)], value),
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u8 => {
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// Ignore write if it falls within the boundaries of OBJ VRAM
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switch (mode) {
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0, 1, 2 => if (0x0001_0000 <= idx) return,
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else => if (0x0001_4000 <= idx) return,
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}
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const align_idx = idx & ~@as(u32, 1); // Aligned to a halfword boundary
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std.mem.writeIntSliceLittle(u16, self.buf[align_idx..][0..@sizeOf(u16)], @as(u16, value) * 0x101);
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},
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else => @compileError("VRAM: Unsupported write width"),
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}
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}
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fn mirror(address: usize) usize {
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// Mirrored in steps of 128K (64K + 32K + 32K) (abcc)
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const addr = address & 0x1FFFF;
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// If the address is within 96K we don't do anything,
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// otherwise we want to mirror the last 32K (addresses between 64K and 96K)
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return if (addr < vram_size) addr else 0x10000 + (addr & 0x7FFF);
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}
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};
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const Oam = struct {
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const oam_size = 0x400;
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const Self = @This();
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buf: []u8,
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allocator: Allocator,
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fn init(allocator: Allocator) !Self {
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const buf = try allocator.alloc(u8, oam_size);
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std.mem.set(u8, buf, 0);
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return Self{
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.buf = buf,
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.allocator = allocator,
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};
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}
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fn deinit(self: *Self) void {
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self.allocator.free(self.buf);
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self.* = undefined;
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}
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pub fn read(self: *const Self, comptime T: type, address: usize) T {
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const addr = address & 0x3FF;
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return switch (T) {
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u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
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else => @compileError("OAM: Unsupported read width"),
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};
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}
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pub fn write(self: *Self, comptime T: type, address: usize, value: T) void {
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const addr = address & 0x3FF;
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switch (T) {
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u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
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u8 => return, // 8-bit writes are explicitly ignored
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else => @compileError("OAM: Unsupported write width"),
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}
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}
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};
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const Window = struct {
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const Self = @This();
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@ -0,0 +1,40 @@
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const std = @import("std");
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const Allocator = std.mem.Allocator;
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const buf_len = 0x400;
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const Self = @This();
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buf: []u8,
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allocator: Allocator,
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pub fn read(self: *const Self, comptime T: type, address: usize) T {
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const addr = address & 0x3FF;
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return switch (T) {
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u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
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else => @compileError("OAM: Unsupported read width"),
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};
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}
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pub fn write(self: *Self, comptime T: type, address: usize, value: T) void {
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const addr = address & 0x3FF;
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switch (T) {
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u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
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u8 => return, // 8-bit writes are explicitly ignored
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else => @compileError("OAM: Unsupported write width"),
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}
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}
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pub fn init(allocator: Allocator) !Self {
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const buf = try allocator.alloc(u8, buf_len);
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std.mem.set(u8, buf, 0);
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return Self{ .buf = buf, .allocator = allocator };
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}
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pub fn deinit(self: *Self) void {
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self.allocator.free(self.buf);
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self.* = undefined;
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}
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@ -0,0 +1,47 @@
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const std = @import("std");
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const Allocator = std.mem.Allocator;
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const buf_len = 0x400;
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const Self = @This();
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buf: []u8,
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allocator: Allocator,
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pub fn read(self: *const Self, comptime T: type, address: usize) T {
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const addr = address & 0x3FF;
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return switch (T) {
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u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
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else => @compileError("PALRAM: Unsupported read width"),
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};
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}
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pub fn write(self: *Self, comptime T: type, address: usize, value: T) void {
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const addr = address & 0x3FF;
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switch (T) {
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u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
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u8 => {
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const align_addr = addr & ~@as(u32, 1); // Aligned to Halfword boundary
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std.mem.writeIntSliceLittle(u16, self.buf[align_addr..][0..@sizeOf(u16)], @as(u16, value) * 0x101);
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},
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else => @compileError("PALRAM: Unsupported write width"),
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}
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}
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pub fn init(allocator: Allocator) !Self {
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const buf = try allocator.alloc(u8, buf_len);
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std.mem.set(u8, buf, 0);
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return Self{ .buf = buf, .allocator = allocator };
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}
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pub fn deinit(self: *Self) void {
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self.allocator.free(self.buf);
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self.* = undefined;
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}
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pub fn backdrop(self: *const Self) u16 {
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return self.read(u16, 0);
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}
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@ -0,0 +1,60 @@
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const std = @import("std");
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const io = @import("../bus/io.zig");
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const Allocator = std.mem.Allocator;
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const buf_len = 0x18000;
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const Self = @This();
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buf: []u8,
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allocator: Allocator,
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pub fn read(self: *const Self, comptime T: type, address: usize) T {
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const addr = Self.mirror(address);
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return switch (T) {
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u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
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else => @compileError("VRAM: Unsupported read width"),
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};
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}
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pub fn write(self: *Self, comptime T: type, dispcnt: io.DisplayControl, address: usize, value: T) void {
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const mode: u3 = dispcnt.bg_mode.read();
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const idx = Self.mirror(address);
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switch (T) {
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u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[idx..][0..@sizeOf(T)], value),
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u8 => {
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// Ignore write if it falls within the boundaries of OBJ VRAM
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switch (mode) {
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0, 1, 2 => if (0x0001_0000 <= idx) return,
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else => if (0x0001_4000 <= idx) return,
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}
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const align_idx = idx & ~@as(u32, 1); // Aligned to a halfword boundary
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std.mem.writeIntSliceLittle(u16, self.buf[align_idx..][0..@sizeOf(u16)], @as(u16, value) * 0x101);
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},
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else => @compileError("VRAM: Unsupported write width"),
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}
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}
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pub fn init(allocator: Allocator) !Self {
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const buf = try allocator.alloc(u8, buf_len);
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std.mem.set(u8, buf, 0);
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return Self{ .buf = buf, .allocator = allocator };
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}
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pub fn deinit(self: *Self) void {
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self.allocator.free(self.buf);
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self.* = undefined;
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}
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fn mirror(address: usize) usize {
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// Mirrored in steps of 128K (64K + 32K + 32K) (abcc)
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const addr = address & 0x1FFFF;
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// If the address is within 96K we don't do anything,
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// otherwise we want to mirror the last 32K (addresses between 64K and 96K)
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return if (addr < buf_len) addr else 0x10000 + (addr & 0x7FFF);
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}
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