chore: change directory structure
This commit is contained in:
118
src/core/cpu/thumb/alu.zig
Normal file
118
src/core/cpu/thumb/alu.zig
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@@ -0,0 +1,118 @@
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
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const adc = @import("../arm/data_processing.zig").adc;
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const sbc = @import("../arm/data_processing.zig").sbc;
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const sub = @import("../arm/data_processing.zig").sub;
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const cmp = @import("../arm/data_processing.zig").cmp;
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const cmn = @import("../arm/data_processing.zig").cmn;
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const setTestOpFlags = @import("../arm/data_processing.zig").setTestOpFlags;
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const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
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const logicalLeft = @import("../barrel_shifter.zig").logicalLeft;
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const logicalRight = @import("../barrel_shifter.zig").logicalRight;
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const arithmeticRight = @import("../barrel_shifter.zig").arithmeticRight;
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const rotateRight = @import("../barrel_shifter.zig").rotateRight;
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pub fn format4(comptime op: u4) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const rs = opcode >> 3 & 0x7;
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const rd = opcode & 0x7;
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const carry = @boolToInt(cpu.cpsr.c.read());
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switch (op) {
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0x0 => {
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// AND
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const result = cpu.r[rd] & cpu.r[rs];
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0x1 => {
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// EOR
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const result = cpu.r[rd] ^ cpu.r[rs];
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0x2 => {
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// LSL
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const result = logicalLeft(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0x3 => {
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// LSR
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const result = logicalRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0x4 => {
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// ASR
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const result = arithmeticRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0x5 => {
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// ADC
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cpu.r[rd] = adc(true, cpu, cpu.r[rd], cpu.r[rs], carry);
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},
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0x6 => {
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// SBC
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cpu.r[rd] = sbc(true, cpu, cpu.r[rd], cpu.r[rs], carry);
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},
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0x7 => {
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// ROR
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const result = rotateRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0x8 => {
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// TST
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const result = cpu.r[rd] & cpu.r[rs];
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setLogicOpFlags(true, cpu, result);
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},
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0x9 => {
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// NEG
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cpu.r[rd] = sub(true, cpu, 0, cpu.r[rs]);
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},
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0xA => {
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// CMP
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cmp(cpu, cpu.r[rd], cpu.r[rs]);
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},
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0xB => {
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// CMN
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cmn(cpu, cpu.r[rd], cpu.r[rs]);
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},
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0xC => {
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// ORR
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const result = cpu.r[rd] | cpu.r[rs];
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0xD => {
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// MUL
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const temp = @as(u64, cpu.r[rs]) * @as(u64, cpu.r[rd]);
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const result = @truncate(u32, temp);
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cpu.r[rd] = result;
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// V is unaffected, assuming similar behaviour to ARMv4 MUL C is undefined
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},
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0xE => {
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// BIC
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const result = cpu.r[rd] & ~cpu.r[rs];
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0xF => {
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// MVN
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const result = ~cpu.r[rs];
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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}
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}
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}.inner;
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}
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94
src/core/cpu/thumb/block_data_transfer.zig
Normal file
94
src/core/cpu/thumb/block_data_transfer.zig
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@@ -0,0 +1,94 @@
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
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pub fn format14(comptime L: bool, comptime R: bool) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
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const count = @boolToInt(R) + countRlist(opcode);
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const start = cpu.r[13] - if (!L) count * 4 else 0;
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var end = cpu.r[13];
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if (L) {
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end += count * 4;
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} else {
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end -= 4;
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}
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var address = start;
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var i: u4 = 0;
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while (i < 8) : (i += 1) {
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if (opcode >> i & 1 == 1) {
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if (L) {
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cpu.r[i] = bus.read(u32, address);
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} else {
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bus.write(u32, address, cpu.r[i]);
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}
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address += 4;
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}
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}
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if (R) {
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if (L) {
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const value = bus.read(u32, address);
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cpu.r[15] = value & 0xFFFF_FFFE;
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} else {
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bus.write(u32, address, cpu.r[14]);
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}
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address += 4;
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}
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cpu.r[13] = if (L) end else start;
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}
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}.inner;
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}
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pub fn format15(comptime L: bool, comptime rb: u3) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
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var address = cpu.r[rb];
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const end_address = cpu.r[rb] + 4 * countRlist(opcode);
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if (opcode & 0xFF == 0) {
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if (L) cpu.r[15] = bus.read(u32, address) else bus.write(u32, address, cpu.r[15] + 4);
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cpu.r[rb] += 0x40;
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return;
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}
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var i: u4 = 0;
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var first_write = true;
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while (i < 8) : (i += 1) {
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if (opcode >> i & 1 == 1) {
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if (L) {
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cpu.r[i] = bus.read(u32, address);
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} else {
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bus.write(u32, address, cpu.r[i]);
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}
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if (!L and first_write) {
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cpu.r[rb] = end_address;
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first_write = false;
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}
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address += 4;
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}
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}
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if (L and opcode >> rb & 1 != 1) cpu.r[rb] = address;
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}
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}.inner;
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}
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inline fn countRlist(opcode: u16) u32 {
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var count: u32 = 0;
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comptime var i: u4 = 0;
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inline while (i < 8) : (i += 1) {
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if (opcode >> (7 - i) & 1 == 1) count += 1;
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}
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return count;
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}
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54
src/core/cpu/thumb/branch.zig
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54
src/core/cpu/thumb/branch.zig
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@@ -0,0 +1,54 @@
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
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const checkCond = @import("../../cpu.zig").checkCond;
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const sext = @import("../../util.zig").sext;
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pub fn format16(comptime cond: u4) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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// B
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const offset = sext(u32, u8, opcode & 0xFF) << 1;
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const should_execute = switch (cond) {
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0xE, 0xF => cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond}),
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else => checkCond(cpu.cpsr, cond),
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};
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if (should_execute) {
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cpu.r[15] = (cpu.r[15] + 2) +% offset;
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}
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}
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}.inner;
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}
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pub fn format18() InstrFn {
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return struct {
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// B but conditional
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const offset = sext(u32, u11, opcode & 0x7FF) << 1;
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cpu.r[15] = (cpu.r[15] + 2) +% offset;
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}
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}.inner;
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}
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pub fn format19(comptime is_low: bool) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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// BL
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const offset = opcode & 0x7FF;
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if (is_low) {
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// Instruction 2
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const old_pc = cpu.r[15];
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cpu.r[15] = cpu.r[14] +% (offset << 1);
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cpu.r[14] = old_pc | 1;
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} else {
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// Instruction 1
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cpu.r[14] = (cpu.r[15] + 2) +% (sext(u32, u11, offset) << 12);
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}
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}
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}.inner;
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}
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122
src/core/cpu/thumb/data_processing.zig
Normal file
122
src/core/cpu/thumb/data_processing.zig
Normal file
@@ -0,0 +1,122 @@
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const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
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const shifter = @import("../barrel_shifter.zig");
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const add = @import("../arm/data_processing.zig").add;
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const sub = @import("../arm/data_processing.zig").sub;
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const cmp = @import("../arm/data_processing.zig").cmp;
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const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
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const log = std.log.scoped(.Thumb1);
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pub fn format1(comptime op: u2, comptime offset: u5) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const rs = opcode >> 3 & 0x7;
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const rd = opcode & 0x7;
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const result = switch (op) {
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0b00 => blk: {
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// LSL
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if (offset == 0) {
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break :blk cpu.r[rs];
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} else {
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break :blk shifter.logicalLeft(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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0b01 => blk: {
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// LSR
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if (offset == 0) {
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cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
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break :blk @as(u32, 0);
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} else {
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break :blk shifter.logicalRight(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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0b10 => blk: {
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// ASR
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if (offset == 0) {
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cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
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break :blk @bitCast(u32, @bitCast(i32, cpu.r[rs]) >> 31);
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} else {
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break :blk shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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else => cpu.panic("[CPU/THUMB.1] 0b{b:0>2} is not a valid op", .{op}),
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};
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// Equivalent to an ARM MOVS
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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}
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}.inner;
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}
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pub fn format2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const rs = opcode >> 3 & 0x7;
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const rd = @truncate(u3, opcode);
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if (is_sub) {
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// SUB
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cpu.r[rd] = if (I) blk: {
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break :blk sub(true, cpu, cpu.r[rs], rn);
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} else blk: {
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break :blk sub(true, cpu, cpu.r[rs], cpu.r[rn]);
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};
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} else {
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// ADD
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cpu.r[rd] = if (I) blk: {
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break :blk add(true, cpu, cpu.r[rs], rn);
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} else blk: {
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break :blk add(true, cpu, cpu.r[rs], cpu.r[rn]);
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};
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}
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}
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}.inner;
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}
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pub fn format3(comptime op: u2, comptime rd: u3) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const offset = @truncate(u8, opcode);
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switch (op) {
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0b00 => {
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// MOV
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cpu.r[rd] = offset;
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setLogicOpFlags(true, cpu, offset);
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},
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0b01 => cmp(cpu, cpu.r[rd], offset), // CMP
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0b10 => cpu.r[rd] = add(true, cpu, cpu.r[rd], offset), // ADD
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0b11 => cpu.r[rd] = sub(true, cpu, cpu.r[rd], offset), // SUB
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}
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}
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}.inner;
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}
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pub fn format12(comptime isSP: bool, comptime rd: u3) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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// ADD
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const left = if (isSP) cpu.r[13] else (cpu.r[15] + 2) & 0xFFFF_FFFD;
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const right = (opcode & 0xFF) << 2;
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const result = left + right;
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cpu.r[rd] = result;
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}
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}.inner;
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}
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pub fn format13(comptime S: bool) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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// ADD
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const offset = (opcode & 0x7F) << 2;
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cpu.r[13] = if (S) cpu.r[13] - offset else cpu.r[13] + offset;
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}
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}.inner;
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}
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149
src/core/cpu/thumb/data_transfer.zig
Normal file
149
src/core/cpu/thumb/data_transfer.zig
Normal file
@@ -0,0 +1,149 @@
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const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
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const rotr = @import("../../util.zig").rotr;
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pub fn format6(comptime rd: u3) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
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// LDR
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const offset = (opcode & 0xFF) << 2;
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cpu.r[rd] = bus.read(u32, (cpu.r[15] + 2 & 0xFFFF_FFFD) + offset);
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}
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}.inner;
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}
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const sext = @import("../../util.zig").sext;
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pub fn format78(comptime op: u2, comptime T: bool) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
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const ro = opcode >> 6 & 0x7;
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const rb = opcode >> 3 & 0x7;
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const rd = opcode & 0x7;
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const address = cpu.r[rb] +% cpu.r[ro];
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if (T) {
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// Format 8
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switch (op) {
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0b00 => {
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// STRH
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bus.write(u16, address, @truncate(u16, cpu.r[rd]));
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},
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0b01 => {
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// LDSB
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cpu.r[rd] = sext(u32, u8, bus.read(u8, address));
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},
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0b10 => {
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// LDRH
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const value = bus.read(u16, address);
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cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
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},
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0b11 => {
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// LDRSH
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cpu.r[rd] = if (address & 1 == 1) blk: {
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break :blk sext(u32, u8, bus.read(u8, address));
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} else blk: {
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break :blk sext(u32, u16, bus.read(u16, address));
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||||
};
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},
|
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}
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} else {
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// Format 7
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switch (op) {
|
||||
0b00 => {
|
||||
// STR
|
||||
bus.write(u32, address, cpu.r[rd]);
|
||||
},
|
||||
0b01 => {
|
||||
// STRB
|
||||
bus.write(u8, address, @truncate(u8, cpu.r[rd]));
|
||||
},
|
||||
0b10 => {
|
||||
// LDR
|
||||
const value = bus.read(u32, address);
|
||||
cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
|
||||
},
|
||||
0b11 => {
|
||||
// LDRB
|
||||
cpu.r[rd] = bus.read(u8, address);
|
||||
},
|
||||
}
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
||||
pub fn format9(comptime B: bool, comptime L: bool, comptime offset: u5) InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
|
||||
const rb = opcode >> 3 & 0x7;
|
||||
const rd = opcode & 0x7;
|
||||
|
||||
if (L) {
|
||||
if (B) {
|
||||
// LDRB
|
||||
const address = cpu.r[rb] + offset;
|
||||
cpu.r[rd] = bus.read(u8, address);
|
||||
} else {
|
||||
// LDR
|
||||
const address = cpu.r[rb] + (@as(u32, offset) << 2);
|
||||
const value = bus.read(u32, address);
|
||||
cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
|
||||
}
|
||||
} else {
|
||||
if (B) {
|
||||
// STRB
|
||||
const address = cpu.r[rb] + offset;
|
||||
bus.write(u8, address, @truncate(u8, cpu.r[rd]));
|
||||
} else {
|
||||
// STR
|
||||
const address = cpu.r[rb] + (@as(u32, offset) << 2);
|
||||
bus.write(u32, address, cpu.r[rd]);
|
||||
}
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
||||
pub fn format10(comptime L: bool, comptime offset: u5) InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
|
||||
const rb = opcode >> 3 & 0x7;
|
||||
const rd = opcode & 0x7;
|
||||
|
||||
const address = cpu.r[rb] + (@as(u6, offset) << 1);
|
||||
|
||||
if (L) {
|
||||
// LDRH
|
||||
const value = bus.read(u16, address);
|
||||
cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
|
||||
} else {
|
||||
// STRH
|
||||
bus.write(u16, address, @truncate(u16, cpu.r[rd]));
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
||||
pub fn format11(comptime L: bool, comptime rd: u3) InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
|
||||
const offset = (opcode & 0xFF) << 2;
|
||||
const address = cpu.r[13] + offset;
|
||||
|
||||
if (L) {
|
||||
// LDR
|
||||
const value = bus.read(u32, address);
|
||||
cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
|
||||
} else {
|
||||
// STR
|
||||
bus.write(u32, address, cpu.r[rd]);
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
36
src/core/cpu/thumb/processing_branch.zig
Normal file
36
src/core/cpu/thumb/processing_branch.zig
Normal file
@@ -0,0 +1,36 @@
|
||||
const Bus = @import("../../Bus.zig");
|
||||
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
|
||||
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
|
||||
|
||||
const cmp = @import("../arm/data_processing.zig").cmp;
|
||||
const add = @import("../arm/data_processing.zig").add;
|
||||
|
||||
pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
const src_idx = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
|
||||
const dst_idx = @as(u4, h1) << 3 | (opcode & 0x7);
|
||||
|
||||
const src = if (src_idx == 0xF) (cpu.r[src_idx] + 2) & 0xFFFF_FFFE else cpu.r[src_idx];
|
||||
const dst = if (dst_idx == 0xF) (cpu.r[dst_idx] + 2) & 0xFFFF_FFFE else cpu.r[dst_idx];
|
||||
|
||||
switch (op) {
|
||||
0b00 => {
|
||||
// ADD
|
||||
const sum = add(false, cpu, dst, src);
|
||||
cpu.r[dst_idx] = if (dst_idx == 0xF) sum & 0xFFFF_FFFE else sum;
|
||||
},
|
||||
0b01 => cmp(cpu, dst, src), // CMP
|
||||
0b10 => {
|
||||
// MOV
|
||||
cpu.r[dst_idx] = if (dst_idx == 0xF) src & 0xFFFF_FFFE else src;
|
||||
},
|
||||
0b11 => {
|
||||
// BX
|
||||
cpu.cpsr.t.write(src & 1 == 1);
|
||||
cpu.r[15] = src & 0xFFFF_FFFE;
|
||||
},
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
22
src/core/cpu/thumb/software_interrupt.zig
Normal file
22
src/core/cpu/thumb/software_interrupt.zig
Normal file
@@ -0,0 +1,22 @@
|
||||
const Bus = @import("../../Bus.zig");
|
||||
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
|
||||
const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
|
||||
|
||||
pub fn thumbSoftwareInterrupt() InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, _: u16) void {
|
||||
// Copy Values from Current Mode
|
||||
const r15 = cpu.r[15];
|
||||
const cpsr = cpu.cpsr.raw;
|
||||
|
||||
// Switch Mode
|
||||
cpu.changeMode(.Supervisor);
|
||||
cpu.cpsr.t.write(false); // Force ARM Mode
|
||||
cpu.cpsr.i.write(true); // Disable normal interrupts
|
||||
|
||||
cpu.r[14] = r15; // Resume Execution
|
||||
cpu.spsr.raw = cpsr; // Previous mode CPSR
|
||||
cpu.r[15] = 0x0000_0008;
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
Reference in New Issue
Block a user