123 lines
4.2 KiB
Zig
123 lines
4.2 KiB
Zig
const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
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const shifter = @import("../barrel_shifter.zig");
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const add = @import("../arm/data_processing.zig").add;
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const sub = @import("../arm/data_processing.zig").sub;
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const cmp = @import("../arm/data_processing.zig").cmp;
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const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
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const log = std.log.scoped(.Thumb1);
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pub fn format1(comptime op: u2, comptime offset: u5) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const rs = opcode >> 3 & 0x7;
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const rd = opcode & 0x7;
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const result = switch (op) {
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0b00 => blk: {
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// LSL
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if (offset == 0) {
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break :blk cpu.r[rs];
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} else {
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break :blk shifter.logicalLeft(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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0b01 => blk: {
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// LSR
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if (offset == 0) {
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cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
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break :blk @as(u32, 0);
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} else {
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break :blk shifter.logicalRight(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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0b10 => blk: {
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// ASR
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if (offset == 0) {
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cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
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break :blk @bitCast(u32, @bitCast(i32, cpu.r[rs]) >> 31);
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} else {
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break :blk shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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else => cpu.panic("[CPU/THUMB.1] 0b{b:0>2} is not a valid op", .{op}),
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};
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// Equivalent to an ARM MOVS
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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}
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}.inner;
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}
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pub fn format2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const rs = opcode >> 3 & 0x7;
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const rd = @truncate(u3, opcode);
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if (is_sub) {
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// SUB
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cpu.r[rd] = if (I) blk: {
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break :blk sub(true, cpu, cpu.r[rs], rn);
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} else blk: {
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break :blk sub(true, cpu, cpu.r[rs], cpu.r[rn]);
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};
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} else {
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// ADD
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cpu.r[rd] = if (I) blk: {
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break :blk add(true, cpu, cpu.r[rs], rn);
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} else blk: {
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break :blk add(true, cpu, cpu.r[rs], cpu.r[rn]);
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};
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}
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}
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}.inner;
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}
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pub fn format3(comptime op: u2, comptime rd: u3) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const offset = @truncate(u8, opcode);
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switch (op) {
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0b00 => {
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// MOV
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cpu.r[rd] = offset;
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setLogicOpFlags(true, cpu, offset);
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},
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0b01 => cmp(cpu, cpu.r[rd], offset), // CMP
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0b10 => cpu.r[rd] = add(true, cpu, cpu.r[rd], offset), // ADD
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0b11 => cpu.r[rd] = sub(true, cpu, cpu.r[rd], offset), // SUB
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}
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}
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}.inner;
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}
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pub fn format12(comptime isSP: bool, comptime rd: u3) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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// ADD
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const left = if (isSP) cpu.r[13] else (cpu.r[15] + 2) & 0xFFFF_FFFD;
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const right = (opcode & 0xFF) << 2;
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const result = left + right;
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cpu.r[rd] = result;
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}
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}.inner;
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}
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pub fn format13(comptime S: bool) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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// ADD
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const offset = (opcode & 0x7F) << 2;
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cpu.r[13] = if (S) cpu.r[13] - offset else cpu.r[13] + offset;
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}
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}.inner;
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}
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