feat: implement Timers

src/Bus.zig

@@ -27,7 +27,7 @@ pub fn init(alloc: Allocator, sched: *Scheduler, rom_path: []const u8, maybe_bio
         .ppu = try Ppu.init(alloc, sched),
         .iwram = try Iwram.init(alloc),
         .ewram = try Ewram.init(alloc),
-        .io = Io.init(),
+        .io = Io.init(sched),
     };
 }
 

src/bus/io.zig

@@ -4,6 +4,8 @@ const Bit = @import("bitfield").Bit;
 const Bitfield = @import("bitfield").Bitfield;
 const Bus = @import("../Bus.zig");
 const DmaController = @import("dma.zig").DmaController;
+const Timer = @import("timer.zig").Timer;
+const Scheduler = @import("../scheduler.zig").Scheduler;
 
 const log = std.log.scoped(.@"I/O");
 
@@ -24,9 +26,16 @@ pub const Io = struct {
     dma2: DmaController(2),
     dma3: DmaController(3),
 
+    // Timers
+    // TODO: Figure out how to turn this into an array
+    tim0: Timer(0),
+    tim1: Timer(1),
+    tim2: Timer(2),
+    tim3: Timer(3),
+
     keyinput: KeyInput,
 
-    pub fn init() Self {
+    pub fn init(sched: *Scheduler) Self {
         return .{
             .ime = false,
             .ie = .{ .raw = 0x0000 },
@@ -35,11 +44,17 @@ pub const Io = struct {
             .postflg = .FirstBoot,
             .haltcnt = .Execute,
 
-            // Dma Transfers
+            // Dma Controllers
             .dma0 = DmaController(0).init(),
             .dma1 = DmaController(1).init(),
             .dma2 = DmaController(2).init(),
             .dma3 = DmaController(3).init(),
+
+            // Timers
+            .tim0 = Timer(0).init(sched),
+            .tim1 = Timer(1).init(sched),
+            .tim2 = Timer(2).init(sched),
+            .tim3 = Timer(3).init(sched),
         };
     }
 
@@ -60,6 +75,10 @@ pub fn read32(bus: *const Bus, addr: u32) u32 {
         0x0400_00C4 => @as(u32, bus.io.dma1.cnt.raw) << 16,
         0x0400_00D0 => @as(u32, bus.io.dma1.cnt.raw) << 16,
         0x0400_00DC => @as(u32, bus.io.dma3.cnt.raw) << 16,
+        0x0400_0100 => @as(u32, bus.io.tim0.cnt.raw) << 16 | bus.io.tim0.counter(),
+        0x0400_0104 => @as(u32, bus.io.tim1.cnt.raw) << 16 | bus.io.tim1.counter(),
+        0x0400_0108 => @as(u32, bus.io.tim2.cnt.raw) << 16 | bus.io.tim2.counter(),
+        0x0400_010C => @as(u32, bus.io.tim3.cnt.raw) << 16 | bus.io.tim3.counter(),
         else => std.debug.panic("Tried to read word from 0x{X:0>8}", .{addr}),
     };
 }
@@ -91,6 +110,10 @@ pub fn write32(bus: *Bus, addr: u32, word: u32) void {
         0x0400_00D4 => bus.io.dma3.writeSad(word),
         0x0400_00D8 => bus.io.dma3.writeDad(word),
         0x0400_00DC => bus.io.dma3.writeCnt(word),
+        0x0400_0100 => bus.io.tim0.writeCnt(word),
+        0x0400_0104 => bus.io.tim1.writeCnt(word),
+        0x0400_0108 => bus.io.tim2.writeCnt(word),
+        0x0400_010C => bus.io.tim3.writeCnt(word),
         0x0400_0200 => bus.io.setIrqs(word),
         0x0400_0204 => log.warn("Wrote 0x{X:0>8} to WAITCNT", .{word}),
         0x0400_0208 => bus.io.ime = word & 1 == 1,
@@ -107,10 +130,14 @@ pub fn read16(bus: *const Bus, addr: u32) u16 {
         0x0400_0200 => bus.io.ie.raw,
         0x0400_0202 => bus.io.irq.raw,
         0x0400_0208 => @boolToInt(bus.io.ime),
-        0x0400_0102 => failedRead("Tried to read halfword from TM0CNT_H", .{}),
+        0x0400_0100 => bus.io.tim0.counter(),
-        0x0400_0106 => failedRead("Tried to read halfword from TM1CNT_H", .{}),
+        0x0400_0102 => bus.io.tim0.cnt.raw,
-        0x0400_010A => failedRead("Tried to read halfword from TM2CNT_H", .{}),
+        0x0400_0104 => bus.io.tim1.counter(),
-        0x0400_010E => failedRead("Tried to read halfword from TM3CNT_H", .{}),
+        0x0400_0106 => bus.io.tim1.cnt.raw,
+        0x0400_0108 => bus.io.tim2.counter(),
+        0x0400_010A => bus.io.tim2.cnt.raw,
+        0x0400_010C => bus.io.tim3.counter(),
+        0x0400_010E => bus.io.tim3.cnt.raw,
         0x0400_0204 => failedRead("Tried to read halfword from WAITCNT", .{}),
         else => std.debug.panic("Tried to read halfword from 0x{X:0>8}", .{addr}),
     };
@@ -153,14 +180,14 @@ pub fn write16(bus: *Bus, addr: u32, halfword: u16) void {
         0x0400_00D2 => bus.io.dma2.writeCntHigh(halfword),
         0x0400_00DC => bus.io.dma3.writeWordCount(halfword),
         0x0400_00DE => bus.io.dma3.writeCntHigh(halfword),
-        0x0400_0100 => log.warn("Wrote 0x{X:0>4} to TM0CNT_L", .{halfword}),
+        0x0400_0100 => bus.io.tim0.writeCntLow(halfword),
-        0x0400_0102 => log.warn("Wrote 0x{X:0>4} to TM0CNT_H", .{halfword}),
+        0x0400_0102 => bus.io.tim0.writeCntHigh(halfword),
-        0x0400_0104 => log.warn("Wrote 0x{X:0>4} to TM1CNT_L", .{halfword}),
+        0x0400_0104 => bus.io.tim1.writeCntLow(halfword),
-        0x0400_0106 => log.warn("Wrote 0x{X:0>4} to TM1CNT_H", .{halfword}),
+        0x0400_0106 => bus.io.tim1.writeCntHigh(halfword),
-        0x0400_0108 => log.warn("Wrote 0x{X:0>4} to TM2CNT_L", .{halfword}),
+        0x0400_0108 => bus.io.tim2.writeCntLow(halfword),
-        0x0400_010A => log.warn("Wrote 0x{X:0>4} to TM2CNT_H", .{halfword}),
+        0x0400_010A => bus.io.tim2.writeCntHigh(halfword),
-        0x0400_010C => log.warn("Wrote 0x{X:0>4} to TM3CNT_L", .{halfword}),
+        0x0400_010C => bus.io.tim3.writeCntLow(halfword),
-        0x0400_010E => log.warn("Wrote 0x{X:0>4} to TM3CNT_H", .{halfword}),
+        0x0400_010E => bus.io.tim3.writeCntHigh(halfword),
         0x0400_0120 => log.warn("Wrote 0x{X:0>4} to SIOMULTI0", .{halfword}),
         0x0400_0122 => log.warn("Wrote 0x{X:0>4} to SIOMULTI1", .{halfword}),
         0x0400_0124 => log.warn("Wrote 0x{X:0>4} to SIOMULTI2", .{halfword}),
@@ -343,3 +370,12 @@ pub const DmaControl = extern union {
     enabled: Bit(u16, 15),
     raw: u16,
 };
+
+/// Read / Write
+pub const TimerControl = extern union {
+    frequency: Bitfield(u16, 0, 2),
+    cascade: Bit(u16, 2),
+    irq: Bit(u16, 6),
+    enabled: Bit(u16, 7),
+    raw: u16,
+};

src/bus/timer.zig

@@ -0,0 +1,131 @@
+const std = @import("std");
+
+const TimerControl = @import("io.zig").TimerControl;
+const Io = @import("io.zig").Io;
+const Scheduler = @import("../scheduler.zig").Scheduler;
+const Event = @import("../scheduler.zig").Event;
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
+
+const log = std.log.scoped(.Timer);
+
+pub fn Timer(comptime id: u2) type {
+    return struct {
+        const Self = @This();
+
+        /// Read Only, Internal. Please use self.counter()
+        _counter: u16,
+
+        /// Write Only, Internal. Please use self.writeCntLow()
+        _reload: u16,
+
+        /// Write Only, Internal. Please use self.WriteCntHigh()
+        cnt: TimerControl,
+
+        /// Internal.
+        sched: *Scheduler,
+
+        /// Internal
+        _start_timestamp: u64,
+
+        pub fn init(sched: *Scheduler) Self {
+            return .{
+                ._reload = 0,
+                ._counter = 0,
+                .cnt = .{ .raw = 0x0000 },
+                .sched = sched,
+                ._start_timestamp = 0,
+            };
+        }
+
+        pub fn counter(self: *const Self) u16 {
+            if (self.cnt.cascade.read())
+                return self._counter
+            else
+                return self._counter +% @truncate(u16, (self.sched.now() - self._start_timestamp) / self.frequency());
+        }
+
+        pub fn writeCnt(self: *Self, word: u32) void {
+            self.writeCntLow(@truncate(u16, word));
+            self.writeCntHigh(@truncate(u16, word >> 16));
+        }
+
+        pub fn writeCntLow(self: *Self, halfword: u16) void {
+            self._reload = halfword;
+        }
+
+        pub fn writeCntHigh(self: *Self, halfword: u16) void {
+            const new = TimerControl{ .raw = halfword };
+
+            // If Timer happens to be enabled, It will either be resheduled or disabled
+            self.sched.removeScheduledEvent(.{ .TimerOverflow = id });
+
+            if (!self.cnt.enabled.read() and new.enabled.read()) {
+                // Reload on Rising edge
+                self._counter = self._reload;
+
+                if (!new.cascade.read()) self.scheduleOverflow();
+            }
+
+            self.cnt.raw = halfword;
+        }
+
+        pub fn handleOverflow(self: *Self, cpu: *Arm7tdmi, io: *Io) void {
+            // Fire IRQ if enabled
+            if (self.cnt.irq.read()) {
+                switch (id) {
+                    0 => io.irq.tim0_overflow.set(),
+                    1 => io.irq.tim1_overflow.set(),
+                    2 => io.irq.tim2_overflow.set(),
+                    3 => io.irq.tim3_overflow.set(),
+                }
+
+                cpu.handleInterrupt();
+            }
+
+            // Perform Cascade Behaviour
+            switch (id) {
+                0 => if (io.tim1.cnt.cascade.read()) {
+                    io.tim1._counter +%= 1;
+
+                    if (io.tim1._counter == 0)
+                        io.tim1.handleOverflow(cpu, io);
+                },
+                1 => if (io.tim2.cnt.cascade.read()) {
+                    io.tim2._counter +%= 1;
+
+                    if (io.tim2._counter == 0)
+                        io.tim2.handleOverflow(cpu, io);
+                },
+                2 => if (io.tim3.cnt.cascade.read()) {
+                    io.tim3._counter +%= 1;
+
+                    if (io.tim3._counter == 0)
+                        io.tim3.handleOverflow(cpu, io);
+                },
+                3 => {}, // There is no Timer for TIM3 to "cascade" to,
+            }
+
+            // Reschedule Timer if we're not cascading
+            if (!self.cnt.cascade.read()) {
+                self._counter = self._reload;
+                self.scheduleOverflow();
+            }
+        }
+
+        fn scheduleOverflow(self: *Self) void {
+            const when = (@as(u64, 0x10000) - self._counter) * self.frequency();
+
+            self._start_timestamp = self.sched.now();
+            self.sched.push(.{ .TimerOverflow = id }, self.sched.now() + when);
+        }
+
+        fn frequency(self: *const Self) u16 {
+            return switch (self.cnt.frequency.read()) {
+                0 => 1,
+                1 => 64,
+                2 => 256,
+                3 => 1024,
+            };
+        }
+    };
+}

src/scheduler.zig

@@ -27,6 +27,10 @@ pub const Scheduler = struct {
         self.queue.deinit();
     }
 
+    pub inline fn now(self: *const Self) u64 {
+        return self.tick;
+    }
+
     pub fn handleEvent(self: *Self, cpu: *Arm7tdmi, bus: *Bus) void {
         const should_handle = if (self.queue.peek()) |e| self.tick >= e.tick else false;
         const stat = &bus.ppu.dispstat;
@@ -39,7 +43,8 @@ pub const Scheduler = struct {
 
             switch (event.kind) {
                 .HeatDeath => {
-                    std.debug.panic("[Scheduler] Somehow, a u64 overflowed", .{});
+                    log.err("A u64 overflowered. This *actually* should never happen.", .{});
+                    unreachable;
                 },
                 .HBlank => {
                     // The End of a Hblank (During Draw or Vblank)
@@ -110,6 +115,35 @@ pub const Scheduler = struct {
                     bus.ppu.dispstat.hblank.set();
                     self.push(.HBlank, self.tick + (68 * 4));
                 },
+                .TimerOverflow => |id| {
+                    // log.warn("TIM{} Overflowed", .{id});
+
+                    switch (id) {
+                        0 => bus.io.tim0.handleOverflow(cpu, &bus.io),
+                        1 => bus.io.tim1.handleOverflow(cpu, &bus.io),
+                        2 => bus.io.tim2.handleOverflow(cpu, &bus.io),
+                        3 => bus.io.tim3.handleOverflow(cpu, &bus.io),
+                    }
+                },
+            }
+        }
+    }
+
+    /// Removes the **first** scheduled event of type `needle` 
+    pub fn removeScheduledEvent(self: *Self, needle: EventKind) void {
+        var it = self.queue.iterator();
+
+        var i: usize = 0;
+        while (it.next()) |event| : (i += 1) {
+            if (std.meta.eql(event.kind, needle)) {
+
+                // This invalidates the iterator
+                _ = self.queue.removeIndex(i);
+
+                // Since removing something from the PQ invalidates the iterator,
+                // this implementation can safely only remove the first instance of
+                // a Scheduled Event. Exit Early
+                break;
             }
         }
     }
@@ -134,9 +168,10 @@ fn lessThan(_: void, a: Event, b: Event) Order {
     return std.math.order(a.tick, b.tick);
 }
 
-pub const EventKind = enum {
+pub const EventKind = union(enum) {
     HeatDeath,
     HBlank,
     VBlank,
     Draw,
+    TimerOverflow: u2,
 };