feat: implement Timers
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cb10dfbdfd
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4a76611fca
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@ -27,7 +27,7 @@ pub fn init(alloc: Allocator, sched: *Scheduler, rom_path: []const u8, maybe_bio
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.ppu = try Ppu.init(alloc, sched),
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.iwram = try Iwram.init(alloc),
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.ewram = try Ewram.init(alloc),
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.io = Io.init(),
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.io = Io.init(sched),
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};
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}
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@ -4,6 +4,8 @@ const Bit = @import("bitfield").Bit;
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const Bitfield = @import("bitfield").Bitfield;
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const Bus = @import("../Bus.zig");
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const DmaController = @import("dma.zig").DmaController;
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const Timer = @import("timer.zig").Timer;
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const Scheduler = @import("../scheduler.zig").Scheduler;
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const log = std.log.scoped(.@"I/O");
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@ -24,9 +26,16 @@ pub const Io = struct {
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dma2: DmaController(2),
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dma3: DmaController(3),
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// Timers
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// TODO: Figure out how to turn this into an array
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tim0: Timer(0),
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tim1: Timer(1),
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tim2: Timer(2),
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tim3: Timer(3),
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keyinput: KeyInput,
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pub fn init() Self {
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pub fn init(sched: *Scheduler) Self {
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return .{
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.ime = false,
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.ie = .{ .raw = 0x0000 },
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@ -35,11 +44,17 @@ pub const Io = struct {
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.postflg = .FirstBoot,
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.haltcnt = .Execute,
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// Dma Transfers
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// Dma Controllers
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.dma0 = DmaController(0).init(),
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.dma1 = DmaController(1).init(),
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.dma2 = DmaController(2).init(),
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.dma3 = DmaController(3).init(),
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// Timers
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.tim0 = Timer(0).init(sched),
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.tim1 = Timer(1).init(sched),
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.tim2 = Timer(2).init(sched),
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.tim3 = Timer(3).init(sched),
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};
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}
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@ -60,6 +75,10 @@ pub fn read32(bus: *const Bus, addr: u32) u32 {
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0x0400_00C4 => @as(u32, bus.io.dma1.cnt.raw) << 16,
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0x0400_00D0 => @as(u32, bus.io.dma1.cnt.raw) << 16,
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0x0400_00DC => @as(u32, bus.io.dma3.cnt.raw) << 16,
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0x0400_0100 => @as(u32, bus.io.tim0.cnt.raw) << 16 | bus.io.tim0.counter(),
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0x0400_0104 => @as(u32, bus.io.tim1.cnt.raw) << 16 | bus.io.tim1.counter(),
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0x0400_0108 => @as(u32, bus.io.tim2.cnt.raw) << 16 | bus.io.tim2.counter(),
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0x0400_010C => @as(u32, bus.io.tim3.cnt.raw) << 16 | bus.io.tim3.counter(),
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else => std.debug.panic("Tried to read word from 0x{X:0>8}", .{addr}),
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};
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}
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@ -91,6 +110,10 @@ pub fn write32(bus: *Bus, addr: u32, word: u32) void {
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0x0400_00D4 => bus.io.dma3.writeSad(word),
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0x0400_00D8 => bus.io.dma3.writeDad(word),
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0x0400_00DC => bus.io.dma3.writeCnt(word),
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0x0400_0100 => bus.io.tim0.writeCnt(word),
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0x0400_0104 => bus.io.tim1.writeCnt(word),
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0x0400_0108 => bus.io.tim2.writeCnt(word),
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0x0400_010C => bus.io.tim3.writeCnt(word),
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0x0400_0200 => bus.io.setIrqs(word),
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0x0400_0204 => log.warn("Wrote 0x{X:0>8} to WAITCNT", .{word}),
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0x0400_0208 => bus.io.ime = word & 1 == 1,
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@ -107,10 +130,14 @@ pub fn read16(bus: *const Bus, addr: u32) u16 {
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0x0400_0200 => bus.io.ie.raw,
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0x0400_0202 => bus.io.irq.raw,
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0x0400_0208 => @boolToInt(bus.io.ime),
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0x0400_0102 => failedRead("Tried to read halfword from TM0CNT_H", .{}),
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0x0400_0106 => failedRead("Tried to read halfword from TM1CNT_H", .{}),
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0x0400_010A => failedRead("Tried to read halfword from TM2CNT_H", .{}),
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0x0400_010E => failedRead("Tried to read halfword from TM3CNT_H", .{}),
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0x0400_0100 => bus.io.tim0.counter(),
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0x0400_0102 => bus.io.tim0.cnt.raw,
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0x0400_0104 => bus.io.tim1.counter(),
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0x0400_0106 => bus.io.tim1.cnt.raw,
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0x0400_0108 => bus.io.tim2.counter(),
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0x0400_010A => bus.io.tim2.cnt.raw,
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0x0400_010C => bus.io.tim3.counter(),
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0x0400_010E => bus.io.tim3.cnt.raw,
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0x0400_0204 => failedRead("Tried to read halfword from WAITCNT", .{}),
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else => std.debug.panic("Tried to read halfword from 0x{X:0>8}", .{addr}),
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};
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@ -153,14 +180,14 @@ pub fn write16(bus: *Bus, addr: u32, halfword: u16) void {
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0x0400_00D2 => bus.io.dma2.writeCntHigh(halfword),
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0x0400_00DC => bus.io.dma3.writeWordCount(halfword),
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0x0400_00DE => bus.io.dma3.writeCntHigh(halfword),
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0x0400_0100 => log.warn("Wrote 0x{X:0>4} to TM0CNT_L", .{halfword}),
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0x0400_0102 => log.warn("Wrote 0x{X:0>4} to TM0CNT_H", .{halfword}),
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0x0400_0104 => log.warn("Wrote 0x{X:0>4} to TM1CNT_L", .{halfword}),
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0x0400_0106 => log.warn("Wrote 0x{X:0>4} to TM1CNT_H", .{halfword}),
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0x0400_0108 => log.warn("Wrote 0x{X:0>4} to TM2CNT_L", .{halfword}),
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0x0400_010A => log.warn("Wrote 0x{X:0>4} to TM2CNT_H", .{halfword}),
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0x0400_010C => log.warn("Wrote 0x{X:0>4} to TM3CNT_L", .{halfword}),
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0x0400_010E => log.warn("Wrote 0x{X:0>4} to TM3CNT_H", .{halfword}),
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0x0400_0100 => bus.io.tim0.writeCntLow(halfword),
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0x0400_0102 => bus.io.tim0.writeCntHigh(halfword),
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0x0400_0104 => bus.io.tim1.writeCntLow(halfword),
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0x0400_0106 => bus.io.tim1.writeCntHigh(halfword),
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0x0400_0108 => bus.io.tim2.writeCntLow(halfword),
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0x0400_010A => bus.io.tim2.writeCntHigh(halfword),
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0x0400_010C => bus.io.tim3.writeCntLow(halfword),
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0x0400_010E => bus.io.tim3.writeCntHigh(halfword),
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0x0400_0120 => log.warn("Wrote 0x{X:0>4} to SIOMULTI0", .{halfword}),
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0x0400_0122 => log.warn("Wrote 0x{X:0>4} to SIOMULTI1", .{halfword}),
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0x0400_0124 => log.warn("Wrote 0x{X:0>4} to SIOMULTI2", .{halfword}),
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@ -343,3 +370,12 @@ pub const DmaControl = extern union {
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enabled: Bit(u16, 15),
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raw: u16,
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};
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/// Read / Write
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pub const TimerControl = extern union {
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frequency: Bitfield(u16, 0, 2),
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cascade: Bit(u16, 2),
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irq: Bit(u16, 6),
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enabled: Bit(u16, 7),
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raw: u16,
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};
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@ -0,0 +1,131 @@
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const std = @import("std");
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const TimerControl = @import("io.zig").TimerControl;
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const Io = @import("io.zig").Io;
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const Scheduler = @import("../scheduler.zig").Scheduler;
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const Event = @import("../scheduler.zig").Event;
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const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
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const log = std.log.scoped(.Timer);
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pub fn Timer(comptime id: u2) type {
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return struct {
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const Self = @This();
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/// Read Only, Internal. Please use self.counter()
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_counter: u16,
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/// Write Only, Internal. Please use self.writeCntLow()
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_reload: u16,
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/// Write Only, Internal. Please use self.WriteCntHigh()
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cnt: TimerControl,
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/// Internal.
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sched: *Scheduler,
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/// Internal
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_start_timestamp: u64,
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pub fn init(sched: *Scheduler) Self {
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return .{
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._reload = 0,
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._counter = 0,
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.cnt = .{ .raw = 0x0000 },
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.sched = sched,
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._start_timestamp = 0,
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};
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}
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pub fn counter(self: *const Self) u16 {
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if (self.cnt.cascade.read())
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return self._counter
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else
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return self._counter +% @truncate(u16, (self.sched.now() - self._start_timestamp) / self.frequency());
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}
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pub fn writeCnt(self: *Self, word: u32) void {
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self.writeCntLow(@truncate(u16, word));
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self.writeCntHigh(@truncate(u16, word >> 16));
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}
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pub fn writeCntLow(self: *Self, halfword: u16) void {
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self._reload = halfword;
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}
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pub fn writeCntHigh(self: *Self, halfword: u16) void {
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const new = TimerControl{ .raw = halfword };
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// If Timer happens to be enabled, It will either be resheduled or disabled
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self.sched.removeScheduledEvent(.{ .TimerOverflow = id });
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if (!self.cnt.enabled.read() and new.enabled.read()) {
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// Reload on Rising edge
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self._counter = self._reload;
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if (!new.cascade.read()) self.scheduleOverflow();
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}
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self.cnt.raw = halfword;
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}
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pub fn handleOverflow(self: *Self, cpu: *Arm7tdmi, io: *Io) void {
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// Fire IRQ if enabled
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if (self.cnt.irq.read()) {
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switch (id) {
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0 => io.irq.tim0_overflow.set(),
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1 => io.irq.tim1_overflow.set(),
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2 => io.irq.tim2_overflow.set(),
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3 => io.irq.tim3_overflow.set(),
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}
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cpu.handleInterrupt();
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}
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// Perform Cascade Behaviour
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switch (id) {
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0 => if (io.tim1.cnt.cascade.read()) {
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io.tim1._counter +%= 1;
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if (io.tim1._counter == 0)
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io.tim1.handleOverflow(cpu, io);
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},
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1 => if (io.tim2.cnt.cascade.read()) {
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io.tim2._counter +%= 1;
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if (io.tim2._counter == 0)
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io.tim2.handleOverflow(cpu, io);
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},
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2 => if (io.tim3.cnt.cascade.read()) {
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io.tim3._counter +%= 1;
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if (io.tim3._counter == 0)
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io.tim3.handleOverflow(cpu, io);
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},
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3 => {}, // There is no Timer for TIM3 to "cascade" to,
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}
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// Reschedule Timer if we're not cascading
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if (!self.cnt.cascade.read()) {
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self._counter = self._reload;
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self.scheduleOverflow();
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}
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}
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fn scheduleOverflow(self: *Self) void {
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const when = (@as(u64, 0x10000) - self._counter) * self.frequency();
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self._start_timestamp = self.sched.now();
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self.sched.push(.{ .TimerOverflow = id }, self.sched.now() + when);
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}
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fn frequency(self: *const Self) u16 {
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return switch (self.cnt.frequency.read()) {
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0 => 1,
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1 => 64,
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2 => 256,
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3 => 1024,
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};
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}
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};
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}
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@ -27,6 +27,10 @@ pub const Scheduler = struct {
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self.queue.deinit();
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}
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pub inline fn now(self: *const Self) u64 {
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return self.tick;
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}
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pub fn handleEvent(self: *Self, cpu: *Arm7tdmi, bus: *Bus) void {
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const should_handle = if (self.queue.peek()) |e| self.tick >= e.tick else false;
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const stat = &bus.ppu.dispstat;
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@ -39,7 +43,8 @@ pub const Scheduler = struct {
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switch (event.kind) {
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.HeatDeath => {
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std.debug.panic("[Scheduler] Somehow, a u64 overflowed", .{});
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log.err("A u64 overflowered. This *actually* should never happen.", .{});
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unreachable;
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},
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.HBlank => {
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// The End of a Hblank (During Draw or Vblank)
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@ -110,6 +115,35 @@ pub const Scheduler = struct {
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bus.ppu.dispstat.hblank.set();
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self.push(.HBlank, self.tick + (68 * 4));
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},
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.TimerOverflow => |id| {
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// log.warn("TIM{} Overflowed", .{id});
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switch (id) {
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0 => bus.io.tim0.handleOverflow(cpu, &bus.io),
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1 => bus.io.tim1.handleOverflow(cpu, &bus.io),
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2 => bus.io.tim2.handleOverflow(cpu, &bus.io),
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3 => bus.io.tim3.handleOverflow(cpu, &bus.io),
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}
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},
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}
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}
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}
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/// Removes the **first** scheduled event of type `needle`
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pub fn removeScheduledEvent(self: *Self, needle: EventKind) void {
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var it = self.queue.iterator();
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var i: usize = 0;
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while (it.next()) |event| : (i += 1) {
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if (std.meta.eql(event.kind, needle)) {
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// This invalidates the iterator
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_ = self.queue.removeIndex(i);
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// Since removing something from the PQ invalidates the iterator,
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// this implementation can safely only remove the first instance of
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// a Scheduled Event. Exit Early
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break;
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}
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}
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}
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@ -134,9 +168,10 @@ fn lessThan(_: void, a: Event, b: Event) Order {
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return std.math.order(a.tick, b.tick);
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}
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pub const EventKind = enum {
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pub const EventKind = union(enum) {
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HeatDeath,
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HBlank,
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VBlank,
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Draw,
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TimerOverflow: u2,
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};
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