paoda/zba
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

feat: implement Timers

Browse Source
This commit is contained in:
Rekai Nyangadzayi Musuka
2022-03-13 05:28:51 -03:00
parent cb10dfbdfd
commit 4a76611fca
4 changed files with 219 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

64
src/bus/io.zig
View File

@@ -4,6 +4,8 @@ const Bit = @import("bitfield").Bit;
const Bitfield = @import("bitfield").Bitfield;
const Bus = @import("../Bus.zig");
const DmaController = @import("dma.zig").DmaController;
const Timer = @import("timer.zig").Timer;
const Scheduler = @import("../scheduler.zig").Scheduler;
const log = std.log.scoped(.@"I/O");
@@ -24,9 +26,16 @@ pub const Io = struct {
dma2: DmaController(2),
dma3: DmaController(3),
// Timers
// TODO: Figure out how to turn this into an array
tim0: Timer(0),
tim1: Timer(1),
tim2: Timer(2),
tim3: Timer(3),
keyinput: KeyInput,
pub fn init() Self {
pub fn init(sched: *Scheduler) Self {
return .{
.ime = false,
.ie = .{ .raw = 0x0000 },
@@ -35,11 +44,17 @@ pub const Io = struct {
.postflg = .FirstBoot,
.haltcnt = .Execute,
// Dma Transfers
// Dma Controllers
.dma0 = DmaController(0).init(),
.dma1 = DmaController(1).init(),
.dma2 = DmaController(2).init(),
.dma3 = DmaController(3).init(),
// Timers
.tim0 = Timer(0).init(sched),
.tim1 = Timer(1).init(sched),
.tim2 = Timer(2).init(sched),
.tim3 = Timer(3).init(sched),
};
}
@@ -60,6 +75,10 @@ pub fn read32(bus: *const Bus, addr: u32) u32 {
0x0400_00C4 => @as(u32, bus.io.dma1.cnt.raw) << 16,
0x0400_00D0 => @as(u32, bus.io.dma1.cnt.raw) << 16,
0x0400_00DC => @as(u32, bus.io.dma3.cnt.raw) << 16,
0x0400_0100 => @as(u32, bus.io.tim0.cnt.raw) << 16 | bus.io.tim0.counter(),
0x0400_0104 => @as(u32, bus.io.tim1.cnt.raw) << 16 | bus.io.tim1.counter(),
0x0400_0108 => @as(u32, bus.io.tim2.cnt.raw) << 16 | bus.io.tim2.counter(),
0x0400_010C => @as(u32, bus.io.tim3.cnt.raw) << 16 | bus.io.tim3.counter(),
else => std.debug.panic("Tried to read word from 0x{X:0>8}", .{addr}),
};
}
@@ -91,6 +110,10 @@ pub fn write32(bus: *Bus, addr: u32, word: u32) void {
0x0400_00D4 => bus.io.dma3.writeSad(word),
0x0400_00D8 => bus.io.dma3.writeDad(word),
0x0400_00DC => bus.io.dma3.writeCnt(word),
0x0400_0100 => bus.io.tim0.writeCnt(word),
0x0400_0104 => bus.io.tim1.writeCnt(word),
0x0400_0108 => bus.io.tim2.writeCnt(word),
0x0400_010C => bus.io.tim3.writeCnt(word),
0x0400_0200 => bus.io.setIrqs(word),
0x0400_0204 => log.warn("Wrote 0x{X:0>8} to WAITCNT", .{word}),
0x0400_0208 => bus.io.ime = word & 1 == 1,
@@ -107,10 +130,14 @@ pub fn read16(bus: *const Bus, addr: u32) u16 {
0x0400_0200 => bus.io.ie.raw,
0x0400_0202 => bus.io.irq.raw,
0x0400_0208 => @boolToInt(bus.io.ime),
0x0400_0102 => failedRead("Tried to read halfword from TM0CNT_H", .{}),
0x0400_0106 => failedRead("Tried to read halfword from TM1CNT_H", .{}),
0x0400_010A => failedRead("Tried to read halfword from TM2CNT_H", .{}),
0x0400_010E => failedRead("Tried to read halfword from TM3CNT_H", .{}),
0x0400_0100 => bus.io.tim0.counter(),
0x0400_0102 => bus.io.tim0.cnt.raw,
0x0400_0104 => bus.io.tim1.counter(),
0x0400_0106 => bus.io.tim1.cnt.raw,
0x0400_0108 => bus.io.tim2.counter(),
0x0400_010A => bus.io.tim2.cnt.raw,
0x0400_010C => bus.io.tim3.counter(),
0x0400_010E => bus.io.tim3.cnt.raw,
0x0400_0204 => failedRead("Tried to read halfword from WAITCNT", .{}),
else => std.debug.panic("Tried to read halfword from 0x{X:0>8}", .{addr}),
};
@@ -153,14 +180,14 @@ pub fn write16(bus: *Bus, addr: u32, halfword: u16) void {
0x0400_00D2 => bus.io.dma2.writeCntHigh(halfword),
0x0400_00DC => bus.io.dma3.writeWordCount(halfword),
0x0400_00DE => bus.io.dma3.writeCntHigh(halfword),
0x0400_0100 => log.warn("Wrote 0x{X:0>4} to TM0CNT_L", .{halfword}),
0x0400_0102 => log.warn("Wrote 0x{X:0>4} to TM0CNT_H", .{halfword}),
0x0400_0104 => log.warn("Wrote 0x{X:0>4} to TM1CNT_L", .{halfword}),
0x0400_0106 => log.warn("Wrote 0x{X:0>4} to TM1CNT_H", .{halfword}),
0x0400_0108 => log.warn("Wrote 0x{X:0>4} to TM2CNT_L", .{halfword}),
0x0400_010A => log.warn("Wrote 0x{X:0>4} to TM2CNT_H", .{halfword}),
0x0400_010C => log.warn("Wrote 0x{X:0>4} to TM3CNT_L", .{halfword}),
0x0400_010E => log.warn("Wrote 0x{X:0>4} to TM3CNT_H", .{halfword}),
0x0400_0100 => bus.io.tim0.writeCntLow(halfword),
0x0400_0102 => bus.io.tim0.writeCntHigh(halfword),
0x0400_0104 => bus.io.tim1.writeCntLow(halfword),
0x0400_0106 => bus.io.tim1.writeCntHigh(halfword),
0x0400_0108 => bus.io.tim2.writeCntLow(halfword),
0x0400_010A => bus.io.tim2.writeCntHigh(halfword),
0x0400_010C => bus.io.tim3.writeCntLow(halfword),
0x0400_010E => bus.io.tim3.writeCntHigh(halfword),
0x0400_0120 => log.warn("Wrote 0x{X:0>4} to SIOMULTI0", .{halfword}),
0x0400_0122 => log.warn("Wrote 0x{X:0>4} to SIOMULTI1", .{halfword}),
0x0400_0124 => log.warn("Wrote 0x{X:0>4} to SIOMULTI2", .{halfword}),
@@ -343,3 +370,12 @@ pub const DmaControl = extern union {
enabled: Bit(u16, 15),
raw: u16,
};
/// Read / Write
pub const TimerControl = extern union {
frequency: Bitfield(u16, 0, 2),
cascade: Bit(u16, 2),
irq: Bit(u16, 6),
enabled: Bit(u16, 7),
raw: u16,
};