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fix: flush pipeline on specific LDR/STR regsiter writes

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-07-13 03:12:20 -03:00
parent 348df3dbe4
commit 27957e1549
1 changed files with 10 additions and 2 deletions
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12
src/cpu/arm/single_data_transfer.zig
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@ -45,8 +45,16 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
}
address = modified_base;
if (W and P or !P) cpu.r[rn] = address;
if (L) cpu.r[rd] = result; // This emulates the LDR rd == rn behaviour
if (W and P or !P) {
cpu.r[rn] = address;
if (rn == 0xF) cpu.pipe.flush();
}
if (L) {
// This emulates the LDR rd == rn behaviour
cpu.r[rd] = result;
if (rd == 0xF) cpu.pipe.flush();
}
}
}.inner;
}