From 27957e154928e7939b1feb388d3b79746690051a Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Wed, 13 Jul 2022 03:12:20 -0300
Subject: [PATCH] fix: flush pipeline on specific LDR/STR regsiter writes

---
 src/cpu/arm/single_data_transfer.zig | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/cpu/arm/single_data_transfer.zig b/src/cpu/arm/single_data_transfer.zig
index d3ca113..3379e86 100644
--- a/src/cpu/arm/single_data_transfer.zig
+++ b/src/cpu/arm/single_data_transfer.zig
@@ -45,8 +45,16 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
             }
 
             address = modified_base;
-            if (W and P or !P) cpu.r[rn] = address;
-            if (L) cpu.r[rd] = result; // This emulates the LDR rd == rn behaviour
+            if (W and P or !P) {
+                cpu.r[rn] = address;
+                if (rn == 0xF) cpu.pipe.flush();
+            }
+
+            if (L) {
+                // This emulates the LDR rd == rn behaviour
+                cpu.r[rd] = result;
+                if (rd == 0xF) cpu.pipe.flush();
+            }
         }
     }.inner;
 }