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style(bus): refactor several hardware abstractions

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This commit is contained in:
Rekai Nyangadzayi Musuka
2022-10-10 10:47:52 -03:00
parent c71e954748
commit 13f6ee8ec4
9 changed files with 266 additions and 258 deletions
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142
src/core/bus/dma.zig
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@@ -40,48 +40,48 @@ pub fn write(comptime T: type, dma: *DmaTuple, addr: u32, value: T) void {
switch (T) {
u32 => switch (byte) {
0xB0 => dma.*[0].setSad(value),
0xB4 => dma.*[0].setDad(value),
0xB8 => dma.*[0].setCnt(value),
0xBC => dma.*[1].setSad(value),
0xC0 => dma.*[1].setDad(value),
0xC4 => dma.*[1].setCnt(value),
0xC8 => dma.*[2].setSad(value),
0xCC => dma.*[2].setDad(value),
0xD0 => dma.*[2].setCnt(value),
0xD4 => dma.*[3].setSad(value),
0xD8 => dma.*[3].setDad(value),
0xDC => dma.*[3].setCnt(value),
0xB0 => dma.*[0].setDmasad(value),
0xB4 => dma.*[0].setDmadad(value),
0xB8 => dma.*[0].setDmacnt(value),
0xBC => dma.*[1].setDmasad(value),
0xC0 => dma.*[1].setDmadad(value),
0xC4 => dma.*[1].setDmacnt(value),
0xC8 => dma.*[2].setDmasad(value),
0xCC => dma.*[2].setDmadad(value),
0xD0 => dma.*[2].setDmacnt(value),
0xD4 => dma.*[3].setDmasad(value),
0xD8 => dma.*[3].setDmadad(value),
0xDC => dma.*[3].setDmacnt(value),
else => util.io.write.undef(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
},
u16 => switch (byte) {
0xB0 => dma.*[0].setSad(setU32L(dma.*[0].sad, value)),
0xB2 => dma.*[0].setSad(setU32H(dma.*[0].sad, value)),
0xB4 => dma.*[0].setDad(setU32L(dma.*[0].dad, value)),
0xB6 => dma.*[0].setDad(setU32H(dma.*[0].dad, value)),
0xB8 => dma.*[0].setCntL(value),
0xBA => dma.*[0].setCntH(value),
0xB0 => dma.*[0].setDmasad(setU32L(dma.*[0].sad, value)),
0xB2 => dma.*[0].setDmasad(setU32H(dma.*[0].sad, value)),
0xB4 => dma.*[0].setDmadad(setU32L(dma.*[0].dad, value)),
0xB6 => dma.*[0].setDmadad(setU32H(dma.*[0].dad, value)),
0xB8 => dma.*[0].setDmacntL(value),
0xBA => dma.*[0].setDmacntH(value),
0xBC => dma.*[1].setSad(setU32L(dma.*[1].sad, value)),
0xBE => dma.*[1].setSad(setU32H(dma.*[1].sad, value)),
0xC0 => dma.*[1].setDad(setU32L(dma.*[1].dad, value)),
0xC2 => dma.*[1].setDad(setU32H(dma.*[1].dad, value)),
0xC4 => dma.*[1].setCntL(value),
0xC6 => dma.*[1].setCntH(value),
0xBC => dma.*[1].setDmasad(setU32L(dma.*[1].sad, value)),
0xBE => dma.*[1].setDmasad(setU32H(dma.*[1].sad, value)),
0xC0 => dma.*[1].setDmadad(setU32L(dma.*[1].dad, value)),
0xC2 => dma.*[1].setDmadad(setU32H(dma.*[1].dad, value)),
0xC4 => dma.*[1].setDmacntL(value),
0xC6 => dma.*[1].setDmacntH(value),
0xC8 => dma.*[2].setSad(setU32L(dma.*[2].sad, value)),
0xCA => dma.*[2].setSad(setU32H(dma.*[2].sad, value)),
0xCC => dma.*[2].setDad(setU32L(dma.*[2].dad, value)),
0xCE => dma.*[2].setDad(setU32H(dma.*[2].dad, value)),
0xD0 => dma.*[2].setCntL(value),
0xD2 => dma.*[2].setCntH(value),
0xC8 => dma.*[2].setDmasad(setU32L(dma.*[2].sad, value)),
0xCA => dma.*[2].setDmasad(setU32H(dma.*[2].sad, value)),
0xCC => dma.*[2].setDmadad(setU32L(dma.*[2].dad, value)),
0xCE => dma.*[2].setDmadad(setU32H(dma.*[2].dad, value)),
0xD0 => dma.*[2].setDmacntL(value),
0xD2 => dma.*[2].setDmacntH(value),
0xD4 => dma.*[3].setSad(setU32L(dma.*[3].sad, value)),
0xD6 => dma.*[3].setSad(setU32H(dma.*[3].sad, value)),
0xD8 => dma.*[3].setDad(setU32L(dma.*[3].dad, value)),
0xDA => dma.*[3].setDad(setU32H(dma.*[3].dad, value)),
0xDC => dma.*[3].setCntL(value),
0xDE => dma.*[3].setCntH(value),
0xD4 => dma.*[3].setDmasad(setU32L(dma.*[3].sad, value)),
0xD6 => dma.*[3].setDmasad(setU32H(dma.*[3].sad, value)),
0xD8 => dma.*[3].setDmadad(setU32L(dma.*[3].dad, value)),
0xDA => dma.*[3].setDmadad(setU32H(dma.*[3].dad, value)),
0xDC => dma.*[3].setDmacntL(value),
0xDE => dma.*[3].setDmacntH(value),
else => util.io.write.undef(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
},
u8 => util.io.write.undef(log, "Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
@@ -110,15 +110,12 @@ fn DmaController(comptime id: u2) type {
cnt: DmaControl,
/// Internal. Currrent Source Address
_sad: u32,
sad_latch: u32,
/// Internal. Current Destination Address
_dad: u32,
dad_latch: u32,
/// Internal. Word Count
_word_count: if (id == 3) u16 else u14,
// Internal. FIFO Word Count
_fifo_word_count: u8,
/// Some DMA Transfers are enabled during Hblank / VBlank and / or
/// have delays. Thefore bit 15 of DMACNT isn't actually something
/// we can use to control when we do or do not execute a step in a DMA Transfer
@@ -132,33 +129,32 @@ fn DmaController(comptime id: u2) type {
.cnt = .{ .raw = 0x000 },
// Internals
._sad = 0,
._dad = 0,
.sad_latch = 0,
.dad_latch = 0,
._word_count = 0,
._fifo_word_count = 4,
.in_progress = false,
};
}
pub fn setSad(self: *Self, addr: u32) void {
pub fn setDmasad(self: *Self, addr: u32) void {
self.sad = addr & sad_mask;
}
pub fn setDad(self: *Self, addr: u32) void {
pub fn setDmadad(self: *Self, addr: u32) void {
self.dad = addr & dad_mask;
}
pub fn setCntL(self: *Self, halfword: u16) void {
pub fn setDmacntL(self: *Self, halfword: u16) void {
self.word_count = @truncate(@TypeOf(self.word_count), halfword);
}
pub fn setCntH(self: *Self, halfword: u16) void {
pub fn setDmacntH(self: *Self, halfword: u16) void {
const new = DmaControl{ .raw = halfword };
if (!self.cnt.enabled.read() and new.enabled.read()) {
// Reload Internals on Rising Edge.
self._sad = self.sad;
self._dad = self.dad;
self.sad_latch = self.sad;
self.dad_latch = self.dad;
self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
// Only a Start Timing of 00 has a DMA Transfer immediately begin
@@ -168,15 +164,15 @@ fn DmaController(comptime id: u2) type {
self.cnt.raw = halfword;
}
pub fn setCnt(self: *Self, word: u32) void {
self.setCntL(@truncate(u16, word));
self.setCntH(@truncate(u16, word >> 16));
pub fn setDmacnt(self: *Self, word: u32) void {
self.setDmacntL(@truncate(u16, word));
self.setDmacntH(@truncate(u16, word >> 16));
}
pub fn step(self: *Self, cpu: *Arm7tdmi) void {
const is_fifo = (id == 1 or id == 2) and self.cnt.start_timing.read() == 0b11;
const sad_adj = Self.adjustment(self.cnt.sad_adj.read());
const dad_adj = if (is_fifo) .Fixed else Self.adjustment(self.cnt.dad_adj.read());
const sad_adj = @intToEnum(Adjustment, self.cnt.sad_adj.read());
const dad_adj = if (is_fifo) .Fixed else @intToEnum(Adjustment, self.cnt.dad_adj.read());
const transfer_type = is_fifo or self.cnt.transfer_type.read();
const offset: u32 = if (transfer_type) @sizeOf(u32) else @sizeOf(u16);
@@ -184,22 +180,22 @@ fn DmaController(comptime id: u2) type {
const mask = if (transfer_type) ~@as(u32, 3) else ~@as(u32, 1);
if (transfer_type) {
cpu.bus.write(u32, self._dad & mask, cpu.bus.read(u32, self._sad & mask));
cpu.bus.write(u32, self.dad_latch & mask, cpu.bus.read(u32, self.sad_latch & mask));
} else {
cpu.bus.write(u16, self._dad & mask, cpu.bus.read(u16, self._sad & mask));
cpu.bus.write(u16, self.dad_latch & mask, cpu.bus.read(u16, self.sad_latch & mask));
}
switch (sad_adj) {
.Increment => self._sad +%= offset,
.Decrement => self._sad -%= offset,
// TODO: Is just ignoring this ok?
.Increment => self.sad_latch +%= offset,
.Decrement => self.sad_latch -%= offset,
// FIXME: Is just ignoring this ok?
.IncrementReload => log.err("{} is a prohibited adjustment on SAD", .{sad_adj}),
.Fixed => {},
}
switch (dad_adj) {
.Increment, .IncrementReload => self._dad +%= offset,
.Decrement => self._dad -%= offset,
.Increment, .IncrementReload => self.dad_latch +%= offset,
.Decrement => self.dad_latch -%= offset,
.Fixed => {},
}
@@ -227,7 +223,7 @@ fn DmaController(comptime id: u2) type {
}
}
pub fn pollBlankingDma(self: *Self, comptime kind: DmaKind) void {
fn poll(self: *Self, comptime kind: DmaKind) void {
if (self.in_progress) return; // If there's an ongoing DMA Transfer, exit early
// No ongoing DMA Transfer, We want to check if we should repeat an existing one
@@ -243,11 +239,11 @@ fn DmaController(comptime id: u2) type {
// Reload internal DAD latch if we are in IncrementRelaod
if (self.in_progress) {
self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
if (Self.adjustment(self.cnt.dad_adj.read()) == .IncrementReload) self._dad = self.dad;
if (@intToEnum(Adjustment, self.cnt.dad_adj.read()) == .IncrementReload) self.dad_latch = self.dad;
}
}
pub fn requestSoundDma(self: *Self, _: u32) void {
pub fn requestAudio(self: *Self, _: u32) void {
comptime std.debug.assert(id == 1 or id == 2);
if (self.in_progress) return; // APU must wait their turn
@@ -259,23 +255,19 @@ fn DmaController(comptime id: u2) type {
// We Assume DMACNT_L is set to 4
// FIXME: Safe to just assume whatever DAD is set to is the FIFO Address?
// self._dad = fifo_addr;
// self.dad_latch = fifo_addr;
self.cnt.repeat.set();
self._word_count = 4;
self.in_progress = true;
}
fn adjustment(idx: u2) Adjustment {
return std.meta.intToEnum(Adjustment, idx) catch unreachable;
}
};
}
pub fn pollBlankingDma(bus: *Bus, comptime kind: DmaKind) void {
bus.dma[0].pollBlankingDma(kind);
bus.dma[1].pollBlankingDma(kind);
bus.dma[2].pollBlankingDma(kind);
bus.dma[3].pollBlankingDma(kind);
pub fn pollDmaOnBlank(bus: *Bus, comptime kind: DmaKind) void {
bus.dma[0].poll(kind);
bus.dma[1].poll(kind);
bus.dma[2].poll(kind);
bus.dma[3].poll(kind);
}
const Adjustment = enum(u2) {