chore: move DMA and Timers from io to bus
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@@ -8,7 +8,25 @@ const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
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const log = std.log.scoped(.Timer);
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pub fn Timer(comptime id: u2) type {
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pub const Timers = struct {
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const Self = @This();
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_0: Timer(0),
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_1: Timer(1),
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_2: Timer(2),
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_3: Timer(3),
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pub fn init(sched: *Scheduler) Self {
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return .{
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._0 = Timer(0).init(sched),
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._1 = Timer(1).init(sched),
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._2 = Timer(2).init(sched),
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._3 = Timer(3).init(sched),
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};
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}
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};
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fn Timer(comptime id: u2) type {
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return struct {
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const Self = @This();
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@@ -69,8 +87,11 @@ pub fn Timer(comptime id: u2) type {
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self.cnt.raw = halfword;
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}
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pub fn handleOverflow(self: *Self, cpu: *Arm7tdmi, io: *Io) void {
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pub fn handleOverflow(self: *Self, cpu: *Arm7tdmi) void {
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// Fire IRQ if enabled
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const io = &cpu.bus.io;
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const tim = &cpu.bus.tim;
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if (self.cnt.irq.read()) {
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switch (id) {
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0 => io.irq.tim0_overflow.set(),
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@@ -84,23 +105,23 @@ pub fn Timer(comptime id: u2) type {
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// Perform Cascade Behaviour
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switch (id) {
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0 => if (io.tim1.cnt.cascade.read()) {
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io.tim1._counter +%= 1;
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0 => if (tim._1.cnt.cascade.read()) {
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tim._1._counter +%= 1;
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if (io.tim1._counter == 0)
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io.tim1.handleOverflow(cpu, io);
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if (tim._1._counter == 0)
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tim._1.handleOverflow(cpu);
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},
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1 => if (io.tim2.cnt.cascade.read()) {
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io.tim2._counter +%= 1;
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1 => if (tim._2.cnt.cascade.read()) {
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tim._2._counter +%= 1;
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if (io.tim2._counter == 0)
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io.tim2.handleOverflow(cpu, io);
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if (tim._2._counter == 0)
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tim._2.handleOverflow(cpu);
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},
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2 => if (io.tim3.cnt.cascade.read()) {
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io.tim3._counter +%= 1;
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2 => if (tim._3.cnt.cascade.read()) {
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tim._3._counter +%= 1;
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if (io.tim3._counter == 0)
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io.tim3.handleOverflow(cpu, io);
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if (tim._3._counter == 0)
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tim._3.handleOverflow(cpu);
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},
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3 => {}, // There is no Timer for TIM3 to "cascade" to,
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}
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