chore: move DMA and Timers from io to bus
This commit is contained in:
126
src/bus/io.zig
126
src/bus/io.zig
@@ -4,7 +4,6 @@ const Bit = @import("bitfield").Bit;
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const Bitfield = @import("bitfield").Bitfield;
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const Bus = @import("../Bus.zig");
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const DmaController = @import("dma.zig").DmaController;
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const Timer = @import("timer.zig").Timer;
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const Scheduler = @import("../scheduler.zig").Scheduler;
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const panic_on_und_io: bool = false;
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@@ -20,24 +19,9 @@ pub const Io = struct {
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irq: InterruptRequest,
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postflg: PostFlag,
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haltcnt: HaltControl,
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// DMA Controllers
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// TODO: Figure out how to turn this into an array
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dma0: DmaController(0),
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dma1: DmaController(1),
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dma2: DmaController(2),
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dma3: DmaController(3),
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// Timers
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// TODO: Figure out how to turn this into an array
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tim0: Timer(0),
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tim1: Timer(1),
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tim2: Timer(2),
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tim3: Timer(3),
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keyinput: KeyInput,
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pub fn init(sched: *Scheduler) Self {
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pub fn init() Self {
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return .{
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.ime = false,
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.ie = .{ .raw = 0x0000 },
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@@ -45,18 +29,6 @@ pub const Io = struct {
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.keyinput = .{ .raw = 0x03FF },
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.postflg = .FirstBoot,
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.haltcnt = .Execute,
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// Dma Controllers
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.dma0 = DmaController(0).init(),
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.dma1 = DmaController(1).init(),
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.dma2 = DmaController(2).init(),
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.dma3 = DmaController(3).init(),
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// Timers
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.tim0 = Timer(0).init(sched),
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.tim1 = Timer(1).init(sched),
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.tim2 = Timer(2).init(sched),
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.tim3 = Timer(3).init(sched),
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};
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}
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@@ -74,16 +46,16 @@ pub fn read32(bus: *const Bus, addr: u32) u32 {
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0x0400_0006 => @as(u32, bus.ppu.bg[0].cnt.raw) << 16 | bus.ppu.vcount.raw,
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// DMA Transfers
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0x0400_00B8 => @as(u32, bus.io.dma0.cnt.raw) << 16,
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0x0400_00C4 => @as(u32, bus.io.dma1.cnt.raw) << 16,
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0x0400_00D0 => @as(u32, bus.io.dma1.cnt.raw) << 16,
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0x0400_00DC => @as(u32, bus.io.dma3.cnt.raw) << 16,
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0x0400_00B8 => @as(u32, bus.dma._0.cnt.raw) << 16,
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0x0400_00C4 => @as(u32, bus.dma._1.cnt.raw) << 16,
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0x0400_00D0 => @as(u32, bus.dma._1.cnt.raw) << 16,
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0x0400_00DC => @as(u32, bus.dma._3.cnt.raw) << 16,
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// Timers
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0x0400_0100 => @as(u32, bus.io.tim0.cnt.raw) << 16 | bus.io.tim0.counter(),
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0x0400_0104 => @as(u32, bus.io.tim1.cnt.raw) << 16 | bus.io.tim1.counter(),
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0x0400_0108 => @as(u32, bus.io.tim2.cnt.raw) << 16 | bus.io.tim2.counter(),
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0x0400_010C => @as(u32, bus.io.tim3.cnt.raw) << 16 | bus.io.tim3.counter(),
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0x0400_0100 => @as(u32, bus.tim._0.cnt.raw) << 16 | bus.tim._0.counter(),
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0x0400_0104 => @as(u32, bus.tim._1.cnt.raw) << 16 | bus.tim._1.counter(),
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0x0400_0108 => @as(u32, bus.tim._2.cnt.raw) << 16 | bus.tim._2.counter(),
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0x0400_010C => @as(u32, bus.tim._3.cnt.raw) << 16 | bus.tim._3.counter(),
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// Interrupts
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0x0400_0200 => @as(u32, bus.io.irq.raw) << 16 | bus.io.ie.raw,
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@@ -112,24 +84,24 @@ pub fn write32(bus: *Bus, addr: u32, word: u32) void {
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0x0400_00A4 => log.warn("Wrote 0x{X:0>8} to FIFO_B", .{word}),
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// DMA Transfers
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0x0400_00B0 => bus.io.dma0.writeSad(word),
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0x0400_00B4 => bus.io.dma0.writeDad(word),
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0x0400_00B8 => bus.io.dma0.writeCnt(word),
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0x0400_00BC => bus.io.dma1.writeSad(word),
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0x0400_00C0 => bus.io.dma1.writeDad(word),
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0x0400_00C4 => bus.io.dma1.writeCnt(word),
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0x0400_00C8 => bus.io.dma2.writeSad(word),
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0x0400_00CC => bus.io.dma2.writeDad(word),
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0x0400_00D0 => bus.io.dma2.writeCnt(word),
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0x0400_00D4 => bus.io.dma3.writeSad(word),
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0x0400_00D8 => bus.io.dma3.writeDad(word),
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0x0400_00DC => bus.io.dma3.writeCnt(word),
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0x0400_00B0 => bus.dma._0.writeSad(word),
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0x0400_00B4 => bus.dma._0.writeDad(word),
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0x0400_00B8 => bus.dma._0.writeCnt(word),
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0x0400_00BC => bus.dma._1.writeSad(word),
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0x0400_00C0 => bus.dma._1.writeDad(word),
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0x0400_00C4 => bus.dma._1.writeCnt(word),
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0x0400_00C8 => bus.dma._2.writeSad(word),
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0x0400_00CC => bus.dma._2.writeDad(word),
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0x0400_00D0 => bus.dma._2.writeCnt(word),
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0x0400_00D4 => bus.dma._3.writeSad(word),
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0x0400_00D8 => bus.dma._3.writeDad(word),
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0x0400_00DC => bus.dma._3.writeCnt(word),
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// Timers
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0x0400_0100 => bus.io.tim0.writeCnt(word),
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0x0400_0104 => bus.io.tim1.writeCnt(word),
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0x0400_0108 => bus.io.tim2.writeCnt(word),
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0x0400_010C => bus.io.tim3.writeCnt(word),
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0x0400_0100 => bus.tim._0.writeCnt(word),
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0x0400_0104 => bus.tim._1.writeCnt(word),
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0x0400_0108 => bus.tim._2.writeCnt(word),
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0x0400_010C => bus.tim._3.writeCnt(word),
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// Serial Communication 1
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0x0400_0120 => log.warn("Wrote 0x{X:0>8} to SIODATA32", .{word}),
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@@ -153,14 +125,14 @@ pub fn read16(bus: *const Bus, addr: u32) u16 {
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0x0400_0088 => bus.apu.bias.raw,
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// Timers
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0x0400_0100 => bus.io.tim0.counter(),
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0x0400_0102 => bus.io.tim0.cnt.raw,
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0x0400_0104 => bus.io.tim1.counter(),
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0x0400_0106 => bus.io.tim1.cnt.raw,
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0x0400_0108 => bus.io.tim2.counter(),
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0x0400_010A => bus.io.tim2.cnt.raw,
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0x0400_010C => bus.io.tim3.counter(),
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0x0400_010E => bus.io.tim3.cnt.raw,
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0x0400_0100 => bus.tim._0.counter(),
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0x0400_0102 => bus.tim._0.cnt.raw,
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0x0400_0104 => bus.tim._1.counter(),
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0x0400_0106 => bus.tim._1.cnt.raw,
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0x0400_0108 => bus.tim._2.counter(),
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0x0400_010A => bus.tim._2.cnt.raw,
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0x0400_010C => bus.tim._3.counter(),
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0x0400_010E => bus.tim._3.cnt.raw,
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// Serial Communication 1
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0x0400_0128 => unimplementedRead("Read halfword from SIOCNT", .{}),
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@@ -216,24 +188,24 @@ pub fn write16(bus: *Bus, addr: u32, halfword: u16) void {
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0x0400_0088 => bus.apu.bias.raw = halfword,
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// Dma Transfers
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0x0400_00B8 => bus.io.dma0.writeWordCount(halfword),
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0x0400_00BA => bus.io.dma0.writeCntHigh(halfword),
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0x0400_00C4 => bus.io.dma1.writeWordCount(halfword),
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0x0400_00C6 => bus.io.dma1.writeCntHigh(halfword),
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0x0400_00D0 => bus.io.dma2.writeWordCount(halfword),
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0x0400_00D2 => bus.io.dma2.writeCntHigh(halfword),
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0x0400_00DC => bus.io.dma3.writeWordCount(halfword),
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0x0400_00DE => bus.io.dma3.writeCntHigh(halfword),
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0x0400_00B8 => bus.dma._0.writeWordCount(halfword),
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0x0400_00BA => bus.dma._0.writeCntHigh(halfword),
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0x0400_00C4 => bus.dma._1.writeWordCount(halfword),
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0x0400_00C6 => bus.dma._1.writeCntHigh(halfword),
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0x0400_00D0 => bus.dma._2.writeWordCount(halfword),
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0x0400_00D2 => bus.dma._2.writeCntHigh(halfword),
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0x0400_00DC => bus.dma._3.writeWordCount(halfword),
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0x0400_00DE => bus.dma._3.writeCntHigh(halfword),
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// Timers
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0x0400_0100 => bus.io.tim0.writeCntLow(halfword),
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0x0400_0102 => bus.io.tim0.writeCntHigh(halfword),
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0x0400_0104 => bus.io.tim1.writeCntLow(halfword),
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0x0400_0106 => bus.io.tim1.writeCntHigh(halfword),
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0x0400_0108 => bus.io.tim2.writeCntLow(halfword),
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0x0400_010A => bus.io.tim2.writeCntHigh(halfword),
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0x0400_010C => bus.io.tim3.writeCntLow(halfword),
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0x0400_010E => bus.io.tim3.writeCntHigh(halfword),
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0x0400_0100 => bus.tim._0.writeCntLow(halfword),
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0x0400_0102 => bus.tim._0.writeCntHigh(halfword),
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0x0400_0104 => bus.tim._1.writeCntLow(halfword),
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0x0400_0106 => bus.tim._1.writeCntHigh(halfword),
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0x0400_0108 => bus.tim._2.writeCntLow(halfword),
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0x0400_010A => bus.tim._2.writeCntHigh(halfword),
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0x0400_010C => bus.tim._3.writeCntLow(halfword),
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0x0400_010E => bus.tim._3.writeCntHigh(halfword),
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// Serial Communication 1
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0x0400_0120 => log.warn("Wrote 0x{X:0>4} to SIOMULTI0", .{halfword}),
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