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fix: incorrect order-of-operations in ARM BL impl

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-04-27 23:15:39 -05:00
parent a87b46898b
commit 002287ecfe
2 changed files with 5 additions and 4 deletions
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7
src/cpu.zig
View File

@ -418,9 +418,10 @@ pub const Arm7tdmi = struct {
if (self.cpsr.t.read()) { if (self.cpsr.t.read()) {
if (opcode >> 11 == 0x1E) { if (opcode >> 11 == 0x1E) {
// Instruction 1 of a BL Opcode, print in ARM mode // Instruction 1 of a BL Opcode, print in ARM mode
const tmp_opcode = self.bus.read(u32, self.r[15] - 2); const other_half = self.bus.debugRead(u16, self.r[15]);
const be_opcode = tmp_opcode << 16 | tmp_opcode >> 16; const bl_opcode = @as(u32, opcode) << 16 | other_half;
log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, be_opcode });
log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, bl_opcode });
} else { } else {
log_str = try std.fmt.bufPrint(&buf, thumb_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode }); log_str = try std.fmt.bufPrint(&buf, thumb_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode });
} }

2
src/cpu/arm/branch.zig
View File

@ -10,7 +10,7 @@ pub fn branch(comptime L: bool) InstrFn {
return struct { return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void { fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
if (L) cpu.r[14] = cpu.r[15]; if (L) cpu.r[14] = cpu.r[15];
cpu.r[15] = cpu.fakePC() +% sext(24, opcode << 2); cpu.r[15] = cpu.fakePC() +% (sext(24, opcode) << 2);
} }
}.inner; }.inner;
} }