137 lines
4.6 KiB
Zig
137 lines
4.6 KiB
Zig
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const std = @import("std");
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const DmaControl = @import("io.zig").DmaControl;
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const Bus = @import("../Bus.zig");
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const log = std.log.scoped(.DmaTransfer);
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/// Function that creates a DMAController. Determines unique DMA Controller behaiour at compile-time
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pub fn DmaController(comptime id: u2) type {
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return struct {
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const Self = @This();
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const sad_mask: u32 = if (id == 0) 0x07FF_FFFF else 0x0FFF_FFFF;
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const dad_mask: u32 = if (id != 3) 0x07FF_FFFF else 0x0FFF_FFFF;
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/// Determines whether DMAController is for DMA0, DMA1, DMA2 or DMA3
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/// Note: Determined at comptime
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id: u2,
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/// Write-only. The first address in a DMA transfer. (DMASAD)
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/// Note: use writeSrc instead of manipulating src_addr directly
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sad: u32,
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/// Write-only. The final address in a DMA transffer. (DMADAD)
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/// Note: Use writeDst instead of manipulatig dst_addr directly
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dad: u32,
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/// Write-only. The Word Count for the DMA Transfer (DMACNT_L)
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word_count: if (id == 3) u16 else u14,
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/// Read / Write. DMACNT_H
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/// Note: Use writeControl instead of manipulating cnt directly.
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cnt: DmaControl,
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/// Internal. Currrent Source Address
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_sad: u32,
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/// Internal. Current Destination Address
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_dad: u32,
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/// Internal. Word Count
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_word_count: if (id == 3) u16 else u14,
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pub fn init() Self {
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return .{
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.id = id,
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.sad = 0,
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.dad = 0,
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.word_count = 0,
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.cnt = .{ .raw = 0x000 },
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// Internals
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._sad = 0,
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._dad = 0,
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._word_count = 0,
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};
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}
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pub fn writeSad(self: *Self, addr: u32) void {
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self.sad = addr & sad_mask;
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}
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pub fn writeDad(self: *Self, addr: u32) void {
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self.dad = addr & dad_mask;
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}
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pub fn writeWordCount(self: *Self, halfword: u16) void {
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self.word_count = @truncate(@TypeOf(self.word_count), halfword);
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}
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pub fn writeCntHigh(self: *Self, halfword: u16) void {
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const new = DmaControl{ .raw = halfword };
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if (!self.cnt.enabled.read() and new.enabled.read()) {
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// Reload Internals on Rising Edge.
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self._sad = self.sad;
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self._dad = self.dad;
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self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
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}
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self.cnt.raw = halfword;
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}
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pub fn writeCnt(self: *Self, word: u32) void {
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self.word_count = @truncate(@TypeOf(self.word_count), word);
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self.writeCntHigh(@truncate(u16, word >> 16));
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}
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pub fn step(self: *Self, bus: *Bus) void {
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const sad_adj = std.meta.intToEnum(Adjustment, self.cnt.sad_adj.read()) catch unreachable;
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const dad_adj = std.meta.intToEnum(Adjustment, self.cnt.dad_adj.read()) catch unreachable;
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var offset: u32 = 0;
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if (self.cnt.transfer_type.read()) {
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offset = @sizeOf(u32); // 32-bit Transfer
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const word = bus.read32(self._sad);
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bus.write32(self._dad, word);
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} else {
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offset = @sizeOf(u16); // 16-bit Transfer
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const halfword = bus.read16(self._sad);
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bus.write16(self._dad, halfword);
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}
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switch (sad_adj) {
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.Increment => self._sad += offset,
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.Decrement => self._sad -= offset,
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.Fixed => {},
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// TODO: Figure out correct behaviour on Illegal Source Addr Control Type
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.IncrementReload => std.debug.panic("panic(DmaTransfer): {} is an illegal src addr adjustment type", .{sad_adj}),
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}
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switch (dad_adj) {
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.Increment, .IncrementReload => self._dad += offset,
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.Decrement => self._dad -= offset,
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.Fixed => {},
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}
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self._word_count -= 1;
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if (self._word_count == 0) {
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if (self.cnt.irq.read()) {
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switch (id) {
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0 => bus.io.irq.dma0.set(),
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1 => bus.io.irq.dma0.set(),
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2 => bus.io.irq.dma0.set(),
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3 => bus.io.irq.dma0.set(),
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}
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}
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self.cnt.enabled.unset();
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}
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}
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};
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}
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const Adjustment = enum(u2) {
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Increment = 0,
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Decrement = 1,
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Fixed = 2,
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IncrementReload = 3,
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};
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