feat: DMA Transfer MVP

src/bus/dma.zig

@@ -0,0 +1,137 @@
+const std = @import("std");
+
+const DmaControl = @import("io.zig").DmaControl;
+const Bus = @import("../Bus.zig");
+
+const log = std.log.scoped(.DmaTransfer);
+
+/// Function that creates a DMAController. Determines unique DMA Controller behaiour at compile-time
+pub fn DmaController(comptime id: u2) type {
+    return struct {
+        const Self = @This();
+
+        const sad_mask: u32 = if (id == 0) 0x07FF_FFFF else 0x0FFF_FFFF;
+        const dad_mask: u32 = if (id != 3) 0x07FF_FFFF else 0x0FFF_FFFF;
+
+        /// Determines whether DMAController is for DMA0, DMA1, DMA2 or DMA3
+        /// Note: Determined at comptime
+        id: u2,
+        /// Write-only. The first address in a DMA transfer. (DMASAD)
+        /// Note: use writeSrc instead of manipulating src_addr directly
+        sad: u32,
+        /// Write-only. The final address in a DMA transffer. (DMADAD)
+        /// Note: Use writeDst instead of manipulatig dst_addr directly
+        dad: u32,
+        /// Write-only. The Word Count for the DMA Transfer (DMACNT_L)
+        word_count: if (id == 3) u16 else u14,
+        /// Read / Write. DMACNT_H
+        /// Note: Use writeControl instead of manipulating cnt directly.
+        cnt: DmaControl,
+
+        /// Internal. Currrent Source Address 
+        _sad: u32,
+        /// Internal. Current Destination Address
+        _dad: u32,
+        /// Internal. Word Count
+        _word_count: if (id == 3) u16 else u14,
+
+        pub fn init() Self {
+            return .{
+                .id = id,
+                .sad = 0,
+                .dad = 0,
+                .word_count = 0,
+                .cnt = .{ .raw = 0x000 },
+
+                // Internals
+                ._sad = 0,
+                ._dad = 0,
+                ._word_count = 0,
+            };
+        }
+
+        pub fn writeSad(self: *Self, addr: u32) void {
+            self.sad = addr & sad_mask;
+        }
+
+        pub fn writeDad(self: *Self, addr: u32) void {
+            self.dad = addr & dad_mask;
+        }
+
+        pub fn writeWordCount(self: *Self, halfword: u16) void {
+            self.word_count = @truncate(@TypeOf(self.word_count), halfword);
+        }
+
+        pub fn writeCntHigh(self: *Self, halfword: u16) void {
+            const new = DmaControl{ .raw = halfword };
+
+            if (!self.cnt.enabled.read() and new.enabled.read()) {
+                // Reload Internals on Rising Edge.
+                self._sad = self.sad;
+                self._dad = self.dad;
+                self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
+            }
+
+            self.cnt.raw = halfword;
+        }
+
+        pub fn writeCnt(self: *Self, word: u32) void {
+            self.word_count = @truncate(@TypeOf(self.word_count), word);
+            self.writeCntHigh(@truncate(u16, word >> 16));
+        }
+
+        pub fn step(self: *Self, bus: *Bus) void {
+            const sad_adj = std.meta.intToEnum(Adjustment, self.cnt.sad_adj.read()) catch unreachable;
+            const dad_adj = std.meta.intToEnum(Adjustment, self.cnt.dad_adj.read()) catch unreachable;
+
+            var offset: u32 = 0;
+
+            if (self.cnt.transfer_type.read()) {
+                offset = @sizeOf(u32); // 32-bit Transfer
+                const word = bus.read32(self._sad);
+                bus.write32(self._dad, word);
+            } else {
+                offset = @sizeOf(u16); // 16-bit Transfer
+                const halfword = bus.read16(self._sad);
+                bus.write16(self._dad, halfword);
+            }
+
+            switch (sad_adj) {
+                .Increment => self._sad += offset,
+                .Decrement => self._sad -= offset,
+                .Fixed => {},
+
+                // TODO: Figure out correct behaviour on Illegal Source Addr Control Type
+                .IncrementReload => std.debug.panic("panic(DmaTransfer): {} is an illegal src addr adjustment type", .{sad_adj}),
+            }
+
+            switch (dad_adj) {
+                .Increment, .IncrementReload => self._dad += offset,
+                .Decrement => self._dad -= offset,
+                .Fixed => {},
+            }
+
+            self._word_count -= 1;
+
+            if (self._word_count == 0) {
+                if (self.cnt.irq.read()) {
+                    switch (id) {
+                        0 => bus.io.irq.dma0.set(),
+                        1 => bus.io.irq.dma0.set(),
+                        2 => bus.io.irq.dma0.set(),
+                        3 => bus.io.irq.dma0.set(),
+                    }
+                }
+
+                self.cnt.enabled.unset();
+            }
+        }
+    };
+}
+
+const Adjustment = enum(u2) {
+    Increment = 0,
+    Decrement = 1,
+    Fixed = 2,
+    IncrementReload = 3,
+};

src/bus/io.zig

@@ -3,6 +3,7 @@ const std = @import("std");
 const Bit = @import("bitfield").Bit;
 const Bitfield = @import("bitfield").Bitfield;
 const Bus = @import("../Bus.zig");
+const DmaController = @import("dma.zig").DmaController;
 
 const log = std.log.scoped(.@"I/O");
 
@@ -16,6 +17,13 @@ pub const Io = struct {
     postflg: PostFlag,
     haltcnt: HaltControl,
 
+    // DMA Controllers
+    // TODO: Figure out how to turn this into an array
+    dma0: DmaController(0),
+    dma1: DmaController(1),
+    dma2: DmaController(2),
+    dma3: DmaController(3),
+
     keyinput: KeyInput,
 
     pub fn init() Self {
@@ -26,6 +34,12 @@ pub const Io = struct {
             .keyinput = .{ .raw = 0x03FF },
             .postflg = .FirstBoot,
             .haltcnt = .Execute,
+
+            // Dma Transfers
+            .dma0 = DmaController(0).init(),
+            .dma1 = DmaController(1).init(),
+            .dma2 = DmaController(2).init(),
+            .dma3 = DmaController(3).init(),
         };
     }
 };
@@ -37,8 +51,10 @@ pub fn read32(bus: *const Bus, addr: u32) u32 {
         0x0400_0006 => @as(u32, bus.ppu.bg[0].cnt.raw) << 16 | bus.ppu.vcount.raw,
         0x0400_0200 => @as(u32, bus.io.irq.raw) << 16 | bus.io.ie.raw,
         0x0400_0208 => @boolToInt(bus.io.ime),
-        0x0400_00C4 => failed_read("Tried to read word from DMA1CNT", .{}),
-        0x0400_00D0 => failed_read("Tried to read word from DMA2CNT", .{}),
+        0x0400_00B8 => @as(u32, bus.io.dma0.cnt.raw) << 16,
+        0x0400_00C4 => @as(u32, bus.io.dma1.cnt.raw) << 16,
+        0x0400_00D0 => @as(u32, bus.io.dma1.cnt.raw) << 16,
+        0x0400_00DC => @as(u32, bus.io.dma3.cnt.raw) << 16,
         else => std.debug.panic("Tried to read word from 0x{X:0>8}", .{addr}),
     };
 }
@@ -74,10 +90,20 @@ pub fn write32(bus: *Bus, addr: u32, word: u32) void {
             bus.ppu.bg[3].hofs.raw = @truncate(u16, word);
             bus.ppu.bg[3].vofs.raw = @truncate(u16, word >> 16);
         },
-        0x0400_00BC => log.warn("Wrote 0x{X:0>8} to DMA1SAD", .{word}),
-        0x0400_00C0 => log.warn("Wrote 0x{X:0>8} to DMA1DAD", .{word}),
-        0x0400_00C8 => log.warn("Wrote 0x{X:0>8} to DMA2SAD", .{word}),
-        0x0400_00CC => log.warn("Wrote 0x{X:0>8} to DMA2DAD", .{word}),
+        0x0400_00A0 => log.warn("Wrote 0x{X:0>8} to FIFO_A", .{word}),
+        0x0400_00A4 => log.warn("Wrote 0x{X:0>8} to FIFO_B", .{word}),
+        0x0400_00B0 => bus.io.dma0.writeSad(word),
+        0x0400_00B4 => bus.io.dma0.writeDad(word),
+        0x0400_00B8 => bus.io.dma0.writeCnt(word),
+        0x0400_00BC => bus.io.dma1.writeSad(word),
+        0x0400_00C0 => bus.io.dma1.writeDad(word),
+        0x0400_00C4 => bus.io.dma1.writeCnt(word),
+        0x0400_00C8 => bus.io.dma2.writeSad(word),
+        0x0400_00CC => bus.io.dma2.writeDad(word),
+        0x0400_00D0 => bus.io.dma2.writeCnt(word),
+        0x0400_00D4 => bus.io.dma3.writeSad(word),
+        0x0400_00D8 => bus.io.dma3.writeDad(word),
+        0x0400_00DC => bus.io.dma3.writeCnt(word),
         0x0400_0200 => {
             bus.io.ie.raw = @truncate(u16, word);
             bus.io.irq.raw &= ~@truncate(u16, word >> 16);
@@ -135,10 +161,10 @@ pub fn write16(bus: *Bus, addr: u32, halfword: u16) void {
         0x0400_0080 => log.warn("Wrote 0x{X:0>4} to SOUNDCNT_L", .{halfword}),
         0x0400_0082 => log.warn("Wrote 0x{X:0>4} to SOUNDCNT_H", .{halfword}),
         0x0400_0084 => log.warn("Wrote 0x{X:0>4} to SOUNDCNT_X", .{halfword}),
-        0x0400_00BA => log.warn("Wrote 0x{X:0>4} to DMA0CNT_H", .{halfword}),
-        0x0400_00C6 => log.warn("Wrote 0x{X:0>4} to DMA1CNT_H", .{halfword}),
-        0x0400_00D2 => log.warn("Wrote 0x{X:0>4} to DMA2CNT_H", .{halfword}),
-        0x0400_00DE => log.warn("Wrote 0x{X:0>4} to DMA3CNT_H", .{halfword}),
+        0x0400_00BA => bus.io.dma0.writeCntHigh(halfword),
+        0x0400_00C6 => bus.io.dma1.writeCntHigh(halfword),
+        0x0400_00D2 => bus.io.dma2.writeCntHigh(halfword),
+        0x0400_00DE => bus.io.dma3.writeCntHigh(halfword),
         0x0400_0100 => log.warn("Wrote 0x{X:0>4} to TM0CNT_L", .{halfword}),
         0x0400_0102 => log.warn("Wrote 0x{X:0>4} to TM0CNT_H", .{halfword}),
         0x0400_0104 => log.warn("Wrote 0x{X:0>4} to TM1CNT_L", .{halfword}),
@@ -316,3 +342,16 @@ const InterruptRequest = extern union {
     game_pak: Bit(u16, 13),
     raw: u16,
 };
+
+/// Read / Write
+pub const DmaControl = extern union {
+    dad_adj: Bitfield(u16, 5, 2),
+    sad_adj: Bitfield(u16, 7, 2),
+    repeat: Bit(u16, 9),
+    transfer_type: Bit(u16, 10),
+    pak_drq: Bit(u16, 11),
+    start_timing: Bitfield(u16, 12, 2),
+    irq: Bit(u16, 14),
+    enabled: Bit(u16, 15),
+    raw: u16,
+};

src/cpu.zig

@@ -246,6 +246,9 @@ pub const Arm7tdmi = struct {
     }
 
     pub fn step(self: *Self) u64 {
+        // If we're processing a DMA (not Sound or Blanking) the CPU is disabled
+        if (self.handleDMATransfers()) return 1;
+
         // If we're halted, the cpu is disabled
         if (self.bus.io.haltcnt == .Halt) return 1;
 
@@ -292,6 +295,35 @@ pub const Arm7tdmi = struct {
         }
     }
 
+    fn handleDMATransfers(self: *Self) bool {
+        const dma0 = &self.bus.io.dma0;
+        const dma1 = &self.bus.io.dma1;
+        const dma2 = &self.bus.io.dma2;
+        const dma3 = &self.bus.io.dma3;
+
+        if (dma0.cnt.enabled.read() and dma0.cnt.start_timing.read() == 0) {
+            dma0.step(self.bus);
+            return true;
+        }
+
+        if (dma1.cnt.enabled.read() and dma1.cnt.start_timing.read() == 0) {
+            dma1.step(self.bus);
+            return true;
+        }
+
+        if (dma2.cnt.enabled.read() and dma2.cnt.start_timing.read() == 0) {
+            dma2.step(self.bus);
+            return true;
+        }
+
+        if (dma3.cnt.enabled.read() and dma3.cnt.start_timing.read() == 0) {
+            dma3.step(self.bus);
+            return true;
+        }
+
+        return false;
+    }
+
     fn thumbFetch(self: *Self) u16 {
         const halfword = self.bus.read16(self.r[15]);
         self.r[15] += 2;