- Winnipeg or Halifax, Canada
- https://musuka.dev
- Joined on
2021-06-29
f38c840d32
Merge pull request 'Draft: Implement Instruction Pipeline' (#3) from pipeline into main
7b146ad7ca
fix(bios): set addr_latch even if bios is skipped
822eed1f3a
fix(bus): make open bus impl aware of CPU pipeline
b37a14900c
style(bus): cpu ptr doesn't need to be optional
f5bd20bc2a
style: code cleanup
Draft: Implement Instruction Pipeline
Draft: Implement Instruction Pipeline
7b146ad7ca
fix(bios): set addr_latch even if bios is skipped
822eed1f3a
fix(bus): make open bus impl aware of CPU pipeline
b37a14900c
style(bus): cpu ptr doesn't need to be optional
f5bd20bc2a
style: code cleanup
d3514b14f3
fix: resolve timing regressions
7142831284
Merge pull request 'Add TOML Support' (#2) from toml into main
97f48c730e
chore(emu): refactor code
293fbd9f55
feat(config): add support for (and read from) TOML config file
622f479e07
feat: parse config.toml in data folder
0204eb6f94
chore: add zig-toml dependency
97f48c730e
chore(emu): refactor code
293fbd9f55
feat(config): add support for (and read from) TOML config file
622f479e07
feat: parse config.toml in data folder
0204eb6f94
chore: add zig-toml dependency
86d2224cfc
chore: update dependencies
86d2224cfc
chore: update dependencies
21eddac31e
style: improve code quality
785135a074
feat: rewrite device ticks
fd38fd6506
style(scheduler): rename scheduler event handlers
bcacac64df
style: code refactoring
924729dcb1
fix(bios): set addr_latch even if bios is skipped
c42004a0b9
fix(bus): make open bus impl aware of CPU pipeline
b280dbfa0e
style(bus): cpu ptr doesn't need to be optional
3e25a7f595
fix: resolve timing regressions
e16c2df8d0
fix: rename Pipline to Pipeline
14ba0dbca9
feat: working pipeline implementation
f466ae2ae2
chore: refactor ARM/THUMB data processing instructions
f616ed29d1
fix: don't flush pipeline when reloading CPSR in ARM Data Processing