71 lines
2.4 KiB
Zig
71 lines
2.4 KiB
Zig
const std = @import("std");
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const util = @import("../util.zig");
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const processor = @import("../cpu.zig");
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const Bus = @import("../bus.zig").Bus;
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const Arm7tdmi = processor.Arm7tdmi;
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const InstrFn = processor.InstrFn;
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pub fn comptimeSingleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {
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return struct {
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fn singleDataTransfer(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
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const rn = opcode >> 16 & 0xF;
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const rd = opcode >> 12 & 0xF;
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const base = cpu.r[rn];
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const offset = if (I) opcode & 0xFFF else registerOffset(cpu, opcode);
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const modified_base = if (U) base + offset else base - offset;
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var address = if (P) modified_base else base;
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if (L) {
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if (B) {
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// LDRB
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cpu.r[rd] = bus.read8(address);
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} else {
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// LDR
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// FIXME: Unsure about how I calculate the boundary offset
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cpu.r[rd] = std.math.rotl(u32, bus.read32(address), address % 4);
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}
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} else {
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if (B) {
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// STRB
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const src = @truncate(u8, cpu.r[rd]);
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bus.write8(address + 3, src);
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bus.write8(address + 2, src);
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bus.write8(address + 1, src);
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bus.write8(address, src);
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} else {
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// STR
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// FIXME: Is this right?
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const src = cpu.r[rd];
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const aligned_addr = address - (address % 4);
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bus.write32(aligned_addr, src);
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}
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}
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address = modified_base;
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if (W and P) cpu.r[rn] = address;
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// TODO: W-bit forces non-privledged mode for the transfer
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}
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}.singleDataTransfer;
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}
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fn registerOffset(cpu: *Arm7tdmi, opcode: u32) u32 {
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const amount = opcode >> 7 & 0x1F;
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const rm = opcode & 0xF;
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const r_val = cpu.r[rm];
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return switch (opcode >> 5 & 0x03) {
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0b00 => r_val << @truncate(u5, amount),
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0b01 => r_val >> @truncate(u5, amount),
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0b10 => @bitCast(u32, @bitCast(i32, r_val) >> @truncate(u5, amount)),
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0b11 => std.math.rotr(u32, r_val, amount),
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else => unreachable,
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};
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}
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