119 lines
4.6 KiB
Zig
119 lines
4.6 KiB
Zig
const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
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const adc = @import("../arm/data_processing.zig").adc;
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const sbc = @import("../arm/data_processing.zig").sbc;
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const sub = @import("../arm/data_processing.zig").sub;
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const cmp = @import("../arm/data_processing.zig").cmp;
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const cmn = @import("../arm/data_processing.zig").cmn;
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const setTestOpFlags = @import("../arm/data_processing.zig").setTestOpFlags;
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const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
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const logicalLeft = @import("../barrel_shifter.zig").logicalLeft;
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const logicalRight = @import("../barrel_shifter.zig").logicalRight;
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const arithmeticRight = @import("../barrel_shifter.zig").arithmeticRight;
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const rotateRight = @import("../barrel_shifter.zig").rotateRight;
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pub fn fmt4(comptime op: u4) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const rs = opcode >> 3 & 0x7;
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const rd = opcode & 0x7;
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const carry = @boolToInt(cpu.cpsr.c.read());
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switch (op) {
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0x0 => {
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// AND
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const result = cpu.r[rd] & cpu.r[rs];
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0x1 => {
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// EOR
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const result = cpu.r[rd] ^ cpu.r[rs];
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0x2 => {
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// LSL
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const result = logicalLeft(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0x3 => {
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// LSR
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const result = logicalRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0x4 => {
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// ASR
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const result = arithmeticRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0x5 => {
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// ADC
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cpu.r[rd] = adc(true, cpu, cpu.r[rd], cpu.r[rs], carry);
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},
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0x6 => {
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// SBC
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cpu.r[rd] = sbc(true, cpu, cpu.r[rd], cpu.r[rs], carry);
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},
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0x7 => {
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// ROR
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const result = rotateRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0x8 => {
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// TST
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const result = cpu.r[rd] & cpu.r[rs];
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setLogicOpFlags(true, cpu, result);
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},
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0x9 => {
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// NEG
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cpu.r[rd] = sub(true, cpu, 0, cpu.r[rs]);
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},
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0xA => {
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// CMP
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cmp(cpu, cpu.r[rd], cpu.r[rs]);
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},
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0xB => {
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// CMN
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cmn(cpu, cpu.r[rd], cpu.r[rs]);
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},
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0xC => {
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// ORR
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const result = cpu.r[rd] | cpu.r[rs];
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0xD => {
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// MUL
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const temp = @as(u64, cpu.r[rs]) * @as(u64, cpu.r[rd]);
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const result = @truncate(u32, temp);
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cpu.r[rd] = result;
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// V is unaffected, assuming similar behaviour to ARMv4 MUL C is undefined
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},
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0xE => {
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// BIC
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const result = cpu.r[rd] & ~cpu.r[rs];
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0xF => {
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// MVN
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const result = ~cpu.r[rs];
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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}
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}
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}.inner;
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}
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