255 lines
9.3 KiB
Zig
255 lines
9.3 KiB
Zig
const std = @import("std");
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const util = @import("../../util.zig");
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const TimerControl = @import("io.zig").TimerControl;
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const Scheduler = @import("../scheduler.zig").Scheduler;
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const Arm7tdmi = @import("arm32").Arm7tdmi;
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const Bus = @import("../Bus.zig");
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const handleInterrupt = @import("../cpu_util.zig").handleInterrupt;
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pub const TimerTuple = struct { Timer(0), Timer(1), Timer(2), Timer(3) };
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const log = std.log.scoped(.Timer);
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const getHalf = util.getHalf;
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const setHalf = util.setHalf;
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pub fn create(sched: *Scheduler) TimerTuple {
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return .{ Timer(0).init(sched), Timer(1).init(sched), Timer(2).init(sched), Timer(3).init(sched) };
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}
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pub fn read(comptime T: type, tim: *const TimerTuple, addr: u32) ?T {
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const nybble_addr: u4 = @truncate(addr);
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return switch (T) {
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u32 => switch (nybble_addr) {
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0x0 => @as(T, tim.*[0].cnt.raw) << 16 | tim.*[0].timcntL(),
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0x4 => @as(T, tim.*[1].cnt.raw) << 16 | tim.*[1].timcntL(),
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0x8 => @as(T, tim.*[2].cnt.raw) << 16 | tim.*[2].timcntL(),
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0xC => @as(T, tim.*[3].cnt.raw) << 16 | tim.*[3].timcntL(),
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else => util.io.read.err(T, log, "unaligned {} read from 0x{X:0>8}", .{ T, addr }),
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},
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u16 => switch (nybble_addr) {
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0x0 => tim.*[0].timcntL(),
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0x2 => tim.*[0].cnt.raw,
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0x4 => tim.*[1].timcntL(),
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0x6 => tim.*[1].cnt.raw,
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0x8 => tim.*[2].timcntL(),
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0xA => tim.*[2].cnt.raw,
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0xC => tim.*[3].timcntL(),
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0xE => tim.*[3].cnt.raw,
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else => util.io.read.err(T, log, "unaligned {} read from 0x{X:0>8}", .{ T, addr }),
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},
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u8 => switch (nybble_addr) {
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0x0, 0x1 => @truncate(tim.*[0].timcntL() >> getHalf(nybble_addr)),
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0x2, 0x3 => @truncate(tim.*[0].cnt.raw >> getHalf(nybble_addr)),
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0x4, 0x5 => @truncate(tim.*[1].timcntL() >> getHalf(nybble_addr)),
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0x6, 0x7 => @truncate(tim.*[1].cnt.raw >> getHalf(nybble_addr)),
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0x8, 0x9 => @truncate(tim.*[2].timcntL() >> getHalf(nybble_addr)),
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0xA, 0xB => @truncate(tim.*[2].cnt.raw >> getHalf(nybble_addr)),
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0xC, 0xD => @truncate(tim.*[3].timcntL() >> getHalf(nybble_addr)),
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0xE, 0xF => @truncate(tim.*[3].cnt.raw >> getHalf(nybble_addr)),
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},
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else => @compileError("TIM: Unsupported read width"),
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};
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}
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pub fn write(comptime T: type, tim: *TimerTuple, addr: u32, value: T) void {
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const nybble_addr: u4 = @truncate(addr);
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return switch (T) {
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u32 => switch (nybble_addr) {
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0x0 => tim.*[0].setTimcnt(value),
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0x4 => tim.*[1].setTimcnt(value),
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0x8 => tim.*[2].setTimcnt(value),
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0xC => tim.*[3].setTimcnt(value),
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else => util.io.write.undef(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
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},
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u16 => switch (nybble_addr) {
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0x0 => tim.*[0].setTimcntL(value),
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0x2 => tim.*[0].setTimcntH(value),
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0x4 => tim.*[1].setTimcntL(value),
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0x6 => tim.*[1].setTimcntH(value),
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0x8 => tim.*[2].setTimcntL(value),
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0xA => tim.*[2].setTimcntH(value),
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0xC => tim.*[3].setTimcntL(value),
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0xE => tim.*[3].setTimcntH(value),
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else => util.io.write.undef(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
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},
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u8 => switch (nybble_addr) {
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0x0, 0x1 => tim.*[0].setTimcntL(setHalf(u16, tim.*[0]._reload, nybble_addr, value)),
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0x2, 0x3 => tim.*[0].setTimcntH(setHalf(u16, tim.*[0].cnt.raw, nybble_addr, value)),
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0x4, 0x5 => tim.*[1].setTimcntL(setHalf(u16, tim.*[1]._reload, nybble_addr, value)),
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0x6, 0x7 => tim.*[1].setTimcntH(setHalf(u16, tim.*[1].cnt.raw, nybble_addr, value)),
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0x8, 0x9 => tim.*[2].setTimcntL(setHalf(u16, tim.*[2]._reload, nybble_addr, value)),
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0xA, 0xB => tim.*[2].setTimcntH(setHalf(u16, tim.*[2].cnt.raw, nybble_addr, value)),
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0xC, 0xD => tim.*[3].setTimcntL(setHalf(u16, tim.*[3]._reload, nybble_addr, value)),
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0xE, 0xF => tim.*[3].setTimcntH(setHalf(u16, tim.*[3].cnt.raw, nybble_addr, value)),
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},
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else => @compileError("TIM: Unsupported write width"),
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};
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}
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fn Timer(comptime id: u2) type {
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return struct {
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const Self = @This();
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/// Read Only, Internal. Please use self.timcntL()
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_counter: u16,
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/// Write Only, Internal. Please use self.setTimcntL()
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_reload: u16,
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/// Write Only, Internal. Please use self.setTimcntH()
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cnt: TimerControl,
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/// Internal.
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sched: *Scheduler,
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/// Internal
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_start_timestamp: u64,
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pub fn init(sched: *Scheduler) Self {
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return .{
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._reload = 0,
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._counter = 0,
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.cnt = .{ .raw = 0x0000 },
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.sched = sched,
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._start_timestamp = 0,
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};
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}
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pub fn reset(self: *Self) void {
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const scheduler = self.sched;
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self.* = Self.init(scheduler);
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}
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/// TIMCNT_L Getter
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pub fn timcntL(self: *const Self) u16 {
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if (self.cnt.cascade.read() or !self.cnt.enabled.read()) return self._counter;
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return self._counter +% @as(u16, @truncate((self.sched.now() - self._start_timestamp) / self.frequency()));
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}
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/// TIMCNT_L Setter
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pub fn setTimcntL(self: *Self, halfword: u16) void {
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self._reload = halfword;
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}
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/// TIMCNT_L & TIMCNT_H
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pub fn setTimcnt(self: *Self, word: u32) void {
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self.setTimcntL(@truncate(word));
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self.setTimcntH(@truncate(word >> 16));
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}
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/// TIMCNT_H
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pub fn setTimcntH(self: *Self, halfword: u16) void {
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const new = TimerControl{ .raw = halfword };
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if (self.cnt.enabled.read()) {
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// timer was already enabled
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// If enabled falling edge or cascade falling edge, timer is paused
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if (!new.enabled.read() or (!self.cnt.cascade.read() and new.cascade.read())) {
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self.sched.removeScheduledEvent(.{ .TimerOverflow = id });
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// Counter should hold the value it stopped at meaning we have to calculate it now
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self._counter +%= @truncate((self.sched.now() - self._start_timestamp) / self.frequency());
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}
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// the timer has always been enabled, but the cascade bit which was blocking the timer has been unset
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if (new.enabled.read() and (self.cnt.cascade.read() and !new.cascade.read())) {
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// we want to reschedule the timer event, however we won't reload the counter.
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// the invariant here is that self._counter holds the already calculated paused value
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self.rescheduleTimerExpire(0);
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}
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} else {
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// the timer was previously disabeld
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if (new.enabled.read()) {
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// timer should start counting (with a reloaded counter value)
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self._counter = self._reload;
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// if cascade happens to be set, the timer doesn't actually do anything though
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if (!new.cascade.read()) self.rescheduleTimerExpire(0);
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}
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}
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self.cnt.raw = halfword;
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}
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pub fn onTimerExpire(self: *Self, cpu: *Arm7tdmi, late: u64) void {
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// Fire IRQ if enabled
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const bus_ptr: *Bus = @ptrCast(@alignCast(cpu.bus.ptr));
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const io = &bus_ptr.io;
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if (self.cnt.irq.read()) {
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switch (id) {
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0 => io.irq.tim0.set(),
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1 => io.irq.tim1.set(),
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2 => io.irq.tim2.set(),
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3 => io.irq.tim3.set(),
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}
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handleInterrupt(cpu);
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}
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// DMA Sound Things
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if (id == 0 or id == 1) {
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bus_ptr.apu.onDmaAudioSampleRequest(cpu, id);
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}
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// Perform Cascade Behaviour
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switch (id) {
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inline 0, 1, 2 => |idx| {
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const next = idx + 1;
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if (bus_ptr.tim[next].cnt.cascade.read()) {
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bus_ptr.tim[next]._counter +%= 1;
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if (bus_ptr.tim[next]._counter == 0) bus_ptr.tim[next].onTimerExpire(cpu, late);
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}
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},
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3 => {}, // THere is no timer for TIM3 to cascade to
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}
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// Reschedule Timer if we're not cascading
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// TIM0 cascade value is N/A
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if (id == 0 or !self.cnt.cascade.read()) {
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self._counter = self._reload;
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self.rescheduleTimerExpire(late);
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}
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}
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fn rescheduleTimerExpire(self: *Self, late: u64) void {
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const when = (@as(u64, 0x10000) - self._counter) * self.frequency();
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self._start_timestamp = self.sched.now();
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self.sched.push(.{ .TimerOverflow = id }, when -| late);
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}
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fn frequency(self: *const Self) u16 {
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return switch (self.cnt.frequency.read()) {
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0 => 1,
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1 => 64,
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2 => 256,
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3 => 1024,
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};
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}
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};
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}
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