428 lines
16 KiB
Zig
428 lines
16 KiB
Zig
const std = @import("std");
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const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
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const Bios = @import("bus/Bios.zig");
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const Ewram = @import("bus/Ewram.zig");
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const GamePak = @import("bus/GamePak.zig");
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const Io = @import("bus/io.zig").Io;
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const Iwram = @import("bus/Iwram.zig");
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const Ppu = @import("ppu.zig").Ppu;
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const Apu = @import("apu.zig").Apu;
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const DmaTuple = @import("bus/dma.zig").DmaTuple;
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const TimerTuple = @import("bus/timer.zig").TimerTuple;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const FilePaths = @import("../util.zig").FilePaths;
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const io = @import("bus/io.zig");
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const Allocator = std.mem.Allocator;
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const log = std.log.scoped(.Bus);
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const createDmaTuple = @import("bus/dma.zig").create;
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const createTimerTuple = @import("bus/timer.zig").create;
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const rotr = @import("../util.zig").rotr;
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const timings: [2][0x10]u8 = [_][0x10]u8{
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// BIOS, Unused, EWRAM, IWRAM, I/0, PALRAM, VRAM, OAM, ROM0, ROM0, ROM1, ROM1, ROM2, ROM2, SRAM, Unused
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[_]u8{ 1, 1, 3, 1, 1, 1, 1, 1, 5, 5, 5, 5, 5, 5, 5, 5 }, // 8-bit & 16-bit
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[_]u8{ 1, 1, 6, 1, 1, 2, 2, 1, 8, 8, 8, 8, 8, 8, 8, 8 }, // 32-bit
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};
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pub const fetch_timings: [2][0x10]u8 = [_][0x10]u8{
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// BIOS, Unused, EWRAM, IWRAM, I/0, PALRAM, VRAM, OAM, ROM0, ROM0, ROM1, ROM1, ROM2, ROM2, SRAM, Unused
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[_]u8{ 1, 1, 3, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 5, 5 }, // 8-bit & 16-bit
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[_]u8{ 1, 1, 6, 1, 1, 2, 2, 1, 4, 4, 4, 4, 4, 4, 8, 8 }, // 32-bit
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};
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// Fastmem Related
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const page_size = 1 * 0x400; // 1KiB
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const address_space_size = 0x1000_0000;
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const table_len = address_space_size / page_size;
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const Self = @This();
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pak: GamePak,
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bios: Bios,
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ppu: Ppu,
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apu: Apu,
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dma: DmaTuple,
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tim: TimerTuple,
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iwram: Iwram,
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ewram: Ewram,
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io: Io,
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cpu: *Arm7tdmi,
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sched: *Scheduler,
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read_table: *const [table_len]?*const anyopaque,
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write_table: *const [table_len]?*anyopaque,
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allocator: Allocator,
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pub fn init(self: *Self, allocator: Allocator, sched: *Scheduler, cpu: *Arm7tdmi, paths: FilePaths) !void {
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const read_table = try allocator.create([table_len]?*const anyopaque);
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const write_table = try allocator.create([table_len]?*anyopaque);
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self.* = .{
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.pak = try GamePak.init(allocator, cpu, paths.rom, paths.save),
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.bios = try Bios.init(allocator, paths.bios),
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.ppu = try Ppu.init(allocator, sched),
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.apu = Apu.init(sched),
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.iwram = try Iwram.init(allocator),
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.ewram = try Ewram.init(allocator),
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.dma = createDmaTuple(),
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.tim = createTimerTuple(sched),
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.io = Io.init(),
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.cpu = cpu,
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.sched = sched,
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.read_table = read_table,
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.write_table = write_table,
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.allocator = allocator,
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};
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// read_table, write_table, and *Self are not restricted to the lifetime
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// of this init function so we can initialize our tables here
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fillReadTable(self, read_table);
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fillWriteTable(self, write_table);
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}
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pub fn deinit(self: *Self) void {
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self.iwram.deinit();
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self.ewram.deinit();
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self.pak.deinit();
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self.bios.deinit();
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self.ppu.deinit();
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self.allocator.destroy(self.read_table);
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self.allocator.destroy(self.write_table);
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self.* = undefined;
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}
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fn fillReadTable(bus: *Self, table: *[table_len]?*const anyopaque) void {
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const vramMirror = @import("ppu.zig").Vram.mirror;
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for (table) |*ptr, i| {
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const addr = page_size * i;
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ptr.* = switch (addr) {
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// General Internal Memory
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0x0000_0000...0x0000_3FFF => null, // BIOS has it's own checks
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0x0200_0000...0x02FF_FFFF => &bus.ewram.buf[addr & 0x3FFFF],
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0x0300_0000...0x03FF_FFFF => &bus.iwram.buf[addr & 0x7FFF],
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0x0400_0000...0x0400_03FF => null, // I/O
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// Internal Display Memory
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0x0500_0000...0x05FF_FFFF => &bus.ppu.palette.buf[addr & 0x3FF],
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0x0600_0000...0x06FF_FFFF => &bus.ppu.vram.buf[vramMirror(addr)],
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0x0700_0000...0x07FF_FFFF => &bus.ppu.oam.buf[addr & 0x3FF],
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// External Memory (Game Pak)
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0x0800_0000...0x0DFF_FFFF => fillTableExternalMemory(bus, addr),
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0x0E00_0000...0x0FFF_FFFF => null, // SRAM
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else => null,
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};
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}
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}
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fn fillWriteTable(bus: *Self, table: *[table_len]?*const anyopaque) void {
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for (table) |*ptr, i| {
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const addr = page_size * i;
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ptr.* = switch (addr) {
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// General Internal Memory
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0x0000_0000...0x0000_3FFF => null, // BIOS has it's own checks
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0x0200_0000...0x02FF_FFFF => &bus.ewram.buf[addr & 0x3FFFF],
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0x0300_0000...0x03FF_FFFF => &bus.iwram.buf[addr & 0x7FFF],
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0x0400_0000...0x0400_03FF => null, // I/O
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// Internal Display Memory
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// FIXME: Different table for different integer width writes?
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0x0500_0000...0x05FF_FFFF => null, // unique behaviour on 8-bit reads
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0x0600_0000...0x06FF_FFFF => null, // Has some behaviour depending on DISPCNT values
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0x0700_0000...0x07FF_FFFF => &bus.ppu.oam.buf[addr & 0x3FF], // 8-bit values ignored
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// External Memory (Game Pak)
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0x0800_0000...0x0DFF_FFFF => null, // ROM
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0x0E00_0000...0x0FFF_FFFF => null, // SRAM
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else => null,
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};
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}
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}
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fn fillTableExternalMemory(bus: *Self, addr: usize) ?*anyopaque {
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// see `GamePak.zig` for more information about what conditions need to be true
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// so that a simple pointer dereference isn't possible
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const start_addr = addr;
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const end_addr = addr + page_size;
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const gpio_data = start_addr <= 0x0800_00C4 and 0x0800_00C4 < end_addr;
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const gpio_direction = start_addr <= 0x0800_00C6 and 0x0800_00C6 < end_addr;
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const gpio_control = start_addr <= 0x0800_00C8 and 0x0800_00C8 < end_addr;
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if (bus.pak.gpio.device.kind != .None and (gpio_data or gpio_direction or gpio_control)) {
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// We found a GPIO device, and this page a GPIO register. We want to handle this in slowmem
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return null;
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}
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if (bus.pak.backup.kind == .Eeprom) {
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if (bus.pak.buf.len > 0x100_000) {
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// We are using a "large" EEPROM which means that if the below check is true
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// this page has an address that's reserved for the EEPROM and therefore must
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// be handled in slowmem
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if (addr & 0x1FF_FFFF > 0x1FF_FEFF) return null;
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} else {
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// We are using a "small" EEPROM which means that if the below check is true
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// (that is, we're in the 0xD address page) then we must handle at least one
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// address in this page in slowmem
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if (@truncate(u4, addr >> 24) == 0xD) return null;
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}
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}
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// Finally, the GamePak has some unique behaviour for reads past the end of the ROM,
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// so those will be handled by slowmem as well
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const masked_addr = addr & 0x1FF_FFFF;
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if (masked_addr >= bus.pak.buf.len) return null;
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return &bus.pak.buf[masked_addr];
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}
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// TODO: Take advantage of fastmem here too?
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pub fn dbgRead(self: *const Self, comptime T: type, unaligned_address: u32) T {
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const page = @truncate(u8, unaligned_address >> 24);
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const address = forceAlign(T, unaligned_address);
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return switch (page) {
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// General Internal Memory
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0x00 => blk: {
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if (address < Bios.size)
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break :blk self.bios.dbgRead(T, self.cpu.r[15], address);
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break :blk self.openBus(T, address);
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},
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0x02 => self.ewram.read(T, address),
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0x03 => self.iwram.read(T, address),
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0x04 => self.readIo(T, address),
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// Internal Display Memory
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0x05 => self.ppu.palette.read(T, address),
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0x06 => self.ppu.vram.read(T, address),
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0x07 => self.ppu.oam.read(T, address),
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// External Memory (Game Pak)
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0x08...0x0D => self.pak.dbgRead(T, address),
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0x0E...0x0F => blk: {
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const value = self.pak.backup.read(unaligned_address);
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const multiplier = switch (T) {
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u32 => 0x01010101,
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u16 => 0x0101,
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u8 => 1,
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else => @compileError("Backup: Unsupported read width"),
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};
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break :blk @as(T, value) * multiplier;
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},
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else => self.openBus(T, address),
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};
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}
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fn readIo(self: *const Self, comptime T: type, address: u32) T {
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return io.read(self, T, address) orelse self.openBus(T, address);
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}
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fn openBus(self: *const Self, comptime T: type, address: u32) T {
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const r15 = self.cpu.r[15];
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const word = blk: {
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// If Arm, get the most recently fetched instruction (PC + 8)
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//
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// FIXME: This is most likely a faulty assumption.
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// I think what *actually* happens is that the Bus has a latch for the most
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// recently fetched piece of data, which is then returned during Open Bus (also DMA open bus?)
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// I can "get away" with this because it's very statistically likely that the most recently latched value is
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// the most recently fetched instruction by the pipeline
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if (!self.cpu.cpsr.t.read()) break :blk self.cpu.pipe.stage[1].?;
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const page = @truncate(u8, r15 >> 24);
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// PC + 2 = stage[0]
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// PC + 4 = stage[1]
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// PC + 6 = Need a Debug Read for this?
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switch (page) {
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// EWRAM, PALRAM, VRAM, and Game ROM (16-bit)
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0x02, 0x05, 0x06, 0x08...0x0D => {
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const halfword: u32 = @truncate(u16, self.cpu.pipe.stage[1].?);
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break :blk halfword << 16 | halfword;
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},
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// BIOS or OAM (32-bit)
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0x00, 0x07 => {
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// Aligned: (PC + 6) | (PC + 4)
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// Unaligned: (PC + 4) | (PC + 2)
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const aligned = address & 3 == 0b00;
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// TODO: What to do on PC + 6?
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const high: u32 = if (aligned) self.dbgRead(u16, r15 + 4) else @truncate(u16, self.cpu.pipe.stage[1].?);
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const low: u32 = @truncate(u16, self.cpu.pipe.stage[@boolToInt(aligned)].?);
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break :blk high << 16 | low;
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},
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// IWRAM (16-bit but special)
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0x03 => {
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// Aligned: (PC + 2) | (PC + 4)
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// Unaligned: (PC + 4) | (PC + 2)
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const aligned = address & 3 == 0b00;
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const high: u32 = @truncate(u16, self.cpu.pipe.stage[1 - @boolToInt(aligned)].?);
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const low: u32 = @truncate(u16, self.cpu.pipe.stage[@boolToInt(aligned)].?);
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break :blk high << 16 | low;
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},
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else => {
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log.err("THUMB open bus read from 0x{X:0>2} page @0x{X:0>8}", .{ page, address });
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@panic("invariant most-likely broken");
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},
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}
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};
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return @truncate(T, word);
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}
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pub fn read(self: *Self, comptime T: type, unaligned_address: u32) T {
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const bits = @typeInfo(std.math.IntFittingRange(0, page_size - 1)).Int.bits;
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const page = unaligned_address >> bits;
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const offset = unaligned_address & (page_size - 1);
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// whether or not we do this in slowmem or fastmem, we should advance the scheduler
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self.sched.tick += timings[@boolToInt(T == u32)][@truncate(u4, page)];
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// We're doing some serious out-of-bounds open-bus reads
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if (page > table_len) return self.slowRead(T, unaligned_address);
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if (self.read_table[page]) |some_ptr| {
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// We have a pointer to a page, cast the pointer to it's underlying type
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const Ptr = [*]const T;
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const alignment = @alignOf(std.meta.Child(Ptr));
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const ptr = @ptrCast(Ptr, @alignCast(alignment, some_ptr));
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// Note: We don't check array length, since we force align the
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// lower bits of the address as the GBA would
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return ptr[forceAlign(T, offset) / @sizeOf(T)];
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}
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return self.slowRead(T, unaligned_address);
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}
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fn slowRead(self: *Self, comptime T: type, unaligned_address: u32) T {
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@setCold(true);
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const page = @truncate(u8, unaligned_address >> 24);
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const address = forceAlign(T, unaligned_address);
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return switch (page) {
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// General Internal Memory
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0x00 => blk: {
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if (address < Bios.size)
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break :blk self.bios.read(T, self.cpu.r[15], address);
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break :blk self.openBus(T, address);
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},
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0x02 => unreachable, // completely handled by fastmeme
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0x03 => unreachable, // completely handled by fastmeme
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0x04 => self.readIo(T, address),
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// Internal Display Memory
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0x05 => unreachable, // completely handled by fastmeme
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0x06 => unreachable, // completely handled by fastmeme
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0x07 => unreachable, // completely handled by fastmeme
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// External Memory (Game Pak)
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0x08...0x0D => self.pak.read(T, address),
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0x0E...0x0F => blk: {
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const value = self.pak.backup.read(unaligned_address);
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const multiplier = switch (T) {
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u32 => 0x01010101,
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u16 => 0x0101,
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u8 => 1,
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else => @compileError("Backup: Unsupported read width"),
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};
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break :blk @as(T, value) * multiplier;
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},
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else => self.openBus(T, address),
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};
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}
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pub fn write(self: *Self, comptime T: type, unaligned_address: u32, value: T) void {
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const bits = @typeInfo(std.math.IntFittingRange(0, page_size - 1)).Int.bits;
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const page = unaligned_address >> bits;
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const offset = unaligned_address & (page_size - 1);
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// whether or not we do this in slowmem or fastmem, we should advance the scheduler
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self.sched.tick += timings[@boolToInt(T == u32)][@truncate(u4, page)];
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// We're doing some serious out-of-bounds open-bus writes, they do nothing though
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if (page > table_len) return;
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if (self.write_table[page]) |some_ptr| {
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// We have a pointer to a page, cast the pointer to it's underlying type
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// 8-bit OAM reads do nothing
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if (T == u8 and @truncate(u8, unaligned_address >> 24) == 0x07) return;
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const Ptr = [*]T;
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const alignment = @alignOf(std.meta.Child(Ptr));
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const ptr = @ptrCast(Ptr, @alignCast(alignment, some_ptr));
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// Note: We don't check array length, since we force align the
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// lower bits of the address as the GBA would
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ptr[forceAlign(T, offset) / @sizeOf(T)] = value;
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} else {
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self.slowWrite(T, unaligned_address, value);
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}
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}
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pub fn slowWrite(self: *Self, comptime T: type, unaligned_address: u32, value: T) void {
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// @setCold(true);
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const page = @truncate(u8, unaligned_address >> 24);
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const address = forceAlign(T, unaligned_address);
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switch (page) {
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// General Internal Memory
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0x00 => self.bios.write(T, address, value),
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0x02 => unreachable, // completely handled by fastmem
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0x03 => unreachable, // completely handled by fastmem
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0x04 => io.write(self, T, address, value),
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// Internal Display Memory
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0x05 => self.ppu.palette.write(T, address, value),
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0x06 => self.ppu.vram.write(T, self.ppu.dispcnt, address, value),
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0x07 => unreachable, // completely handled by fastmem (TODO: Is it faster if I dont?)
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// External Memory (Game Pak)
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0x08...0x0D => self.pak.write(T, self.dma[3].word_count, address, value),
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0x0E...0x0F => self.pak.backup.write(unaligned_address, @truncate(u8, rotr(T, value, 8 * rotateBy(T, unaligned_address)))),
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else => {},
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}
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}
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inline fn rotateBy(comptime T: type, address: u32) u32 {
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return switch (T) {
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u32 => address & 3,
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u16 => address & 1,
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u8 => 0,
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else => @compileError("Backup: Unsupported write width"),
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};
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}
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inline fn forceAlign(comptime T: type, address: u32) u32 {
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return switch (T) {
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u32 => address & ~@as(u32, 3),
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u16 => address & ~@as(u32, 1),
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u8 => address,
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else => @compileError("Bus: Invalid read/write type"),
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};
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}
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