203 lines
6.4 KiB
Zig
203 lines
6.4 KiB
Zig
const std = @import("std");
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const util = @import("util.zig");
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const bitfield = @import("bitfield");
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const BarrelShifter = @import("cpu/barrel_shifter.zig");
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const Bus = @import("bus.zig").Bus;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const Bitfield = bitfield.Bitfield;
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const Bit = bitfield.Bit;
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const comptimeDataProcessing = @import("cpu/data_processing.zig").comptimeDataProcessing;
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const comptimeSingleDataTransfer = @import("cpu/single_data_transfer.zig").comptimeSingleDataTransfer;
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const comptimeHalfSignedDataTransfer = @import("cpu/half_signed_data_transfer.zig").comptimeHalfSignedDataTransfer;
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pub const InstrFn = fn (*Arm7tdmi, *Bus, u32) void;
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const arm_lut: [0x1000]InstrFn = populate();
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pub const Arm7tdmi = struct {
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r: [16]u32,
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sched: *Scheduler,
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bus: *Bus,
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cpsr: CPSR,
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pub fn init(sched: *Scheduler, bus: *Bus) @This() {
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return .{
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.r = [_]u32{0x00} ** 16,
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.sched = sched,
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.bus = bus,
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.cpsr = .{ .raw = 0x0000_00DF },
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};
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}
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pub fn skipBios(self: *@This()) void {
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self.r[0] = 0x08000000;
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self.r[1] = 0x000000EA;
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// GPRs 2 -> 12 *should* already be 0 initialized
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self.r[13] = 0x0300_7F00;
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self.r[14] = 0x0000_0000;
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self.r[15] = 0x0800_0000;
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// TODO: Set sp_irq = 0x0300_7FA0, sp_svc = 0x0300_7FE0
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self.cpsr.raw = 0x6000001F;
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}
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pub inline fn step(self: *@This()) u64 {
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const opcode = self.fetch();
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// self.mgbaLog(opcode);
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if (checkCond(&self.cpsr, opcode)) arm_lut[armIdx(opcode)](self, self.bus, opcode);
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return 1;
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}
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fn fetch(self: *@This()) u32 {
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const word = self.bus.read32(self.r[15]);
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self.r[15] += 4;
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return word;
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}
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fn fakePC(self: *const @This()) u32 {
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return self.r[15] + 4;
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}
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fn mgbaLog(self: *const @This(), opcode: u32) void {
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const stderr = std.io.getStdErr().writer();
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std.debug.getStderrMutex().lock();
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defer std.debug.getStderrMutex().unlock();
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const r0 = self.r[0];
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const r1 = self.r[1];
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const r2 = self.r[2];
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const r3 = self.r[3];
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const r4 = self.r[4];
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const r5 = self.r[5];
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const r6 = self.r[6];
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const r7 = self.r[7];
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const r8 = self.r[8];
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const r9 = self.r[9];
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const r10 = self.r[10];
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const r11 = self.r[11];
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const r12 = self.r[12];
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const r13 = self.r[13];
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const r14 = self.r[14];
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const r15 = self.r[15];
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const cpsr = self.cpsr.raw;
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nosuspend stderr.print("{X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} cpsr: {X:0>8} | {X:0>8}:\n", .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, cpsr, opcode }) catch return;
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}
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};
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fn armIdx(opcode: u32) u12 {
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return @truncate(u12, opcode >> 20 & 0xFF) << 4 | @truncate(u12, opcode >> 4 & 0xF);
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}
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fn checkCond(cpsr: *const CPSR, opcode: u32) bool {
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// TODO: Should I implement an enum?
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return switch (@truncate(u4, opcode >> 28)) {
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0x0 => cpsr.z.read(), // EQ - Equal
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0x1 => !cpsr.z.read(), // NEQ - Not equal
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0x2 => cpsr.c.read(), // CS - Unsigned higher or same
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0x3 => !cpsr.c.read(), // CC - Unsigned lower
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0x4 => cpsr.n.read(), // MI - Negative
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0x5 => !cpsr.n.read(), // PL - Positive or zero
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0x6 => cpsr.v.read(), // VS - Overflow
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0x7 => !cpsr.v.read(), // VC - No overflow
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0x8 => cpsr.c.read() and !cpsr.z.read(), // HI - unsigned higher
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0x9 => !cpsr.c.read() and cpsr.z.read(), // LS - unsigned lower or same
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0xA => cpsr.n.read() == cpsr.v.read(), // GE - Greater or equal
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0xB => cpsr.n.read() != cpsr.v.read(), // LT - Less than
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0xC => !cpsr.z.read() and (cpsr.n.read() == cpsr.z.read()), // GT - Greater than
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0xD => cpsr.z.read() or (cpsr.n.read() != cpsr.v.read()), // LE - Less than or equal
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0xE => true, // AL - Always
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0xF => std.debug.panic("[CPU] 0xF is a reserved condition field", .{}),
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};
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}
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fn populate() [0x1000]InstrFn {
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return comptime {
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@setEvalBranchQuota(0x5000); // TODO: Figure out exact size
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var lut = [_]InstrFn{undefinedInstruction} ** 0x1000;
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var i: usize = 0;
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while (i < lut.len) : (i += 1) {
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if (i >> 10 & 0x3 == 0b00) {
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const I = i >> 9 & 1 == 1;
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const S = i >> 4 & 1 == 1;
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const instrKind = i >> 5 & 0xF;
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lut[i] = comptimeDataProcessing(I, S, instrKind);
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}
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if (i >> 9 & 0x7 == 0b000 and i >> 3 & 1 == 1 and i & 1 == 1) {
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const P = i >> 8 & 1 == 1;
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const U = i >> 7 & 1 == 1;
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const I = i >> 6 & 1 == 1;
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const W = i >> 5 & 1 == 1;
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const L = i >> 4 & 1 == 1;
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lut[i] = comptimeHalfSignedDataTransfer(P, U, I, W, L);
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}
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if (i >> 10 & 0x3 == 0b01) {
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const I = i >> 9 & 1 == 1;
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const P = i >> 8 & 1 == 1;
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const U = i >> 7 & 1 == 1;
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const B = i >> 6 & 1 == 1;
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const W = i >> 5 & 1 == 1;
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const L = i >> 4 & 1 == 1;
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lut[i] = comptimeSingleDataTransfer(I, P, U, B, W, L);
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}
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if (i >> 9 & 0x7 == 0b101) {
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const L = i >> 8 & 1 == 1;
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lut[i] = comptimeBranch(L);
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}
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}
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return lut;
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};
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}
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pub const CPSR = extern union {
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mode: Bitfield(u32, 0, 5),
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t: Bit(u32, 5),
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f: Bit(u32, 6),
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i: Bit(u32, 7),
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v: Bit(u32, 28),
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c: Bit(u32, 29),
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z: Bit(u32, 30),
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n: Bit(u32, 31),
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raw: u32,
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};
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const Mode = enum(u5) {
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User = 0b10000,
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FIQ = 0b10001,
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IRQ = 0b10010,
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Supervisor = 0b10011,
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Abort = 0b10111,
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Undefined = 0b11011,
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System = 0b11111,
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};
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fn undefinedInstruction(_: *Arm7tdmi, _: *Bus, opcode: u32) void {
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const id = armIdx(opcode);
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std.debug.panic("[CPU] {{0x{X:}}} 0x{X:} is an illegal opcode", .{ id, opcode });
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}
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fn comptimeBranch(comptime L: bool) InstrFn {
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return struct {
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fn branch(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
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if (L) {
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cpu.r[14] = cpu.r[15] - 4;
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}
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cpu.r[15] = cpu.fakePC() +% util.u32SignExtend(24, opcode << 2);
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}
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}.branch;
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}
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