Rekai Musuka
9b6118fffb
I believe this to be necessary in order to get hardware interrupts working. thumb.gba test 108 fails but I'm committing anyways (despite the regression) because this is kind of rebase/merge hell and I have something that at least sort of works rn
460 lines
16 KiB
Zig
460 lines
16 KiB
Zig
const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").arm.InstrFn;
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const rotateRight = @import("../barrel_shifter.zig").rotateRight;
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const execute = @import("../barrel_shifter.zig").execute;
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pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
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const rd = @truncate(u4, opcode >> 12 & 0xF);
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const rn = opcode >> 16 & 0xF;
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const old_carry = @boolToInt(cpu.cpsr.c.read());
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// If certain conditions are met, PC is 12 ahead instead of 8
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// TODO: Why these conditions?
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if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
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const op1 = cpu.r[rn];
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const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
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const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
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// Undo special condition from above
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if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
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var result: u32 = undefined;
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var didOverflow: bool = undefined;
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// Perform Data Processing Logic
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switch (kind) {
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0x0 => result = op1 & op2, // AND
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0x1 => result = op1 ^ op2, // EOR
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0x2 => result = op1 -% op2, // SUB
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0x3 => result = op2 -% op1, // RSB
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0x4 => result = newAdd(&didOverflow, op1, op2), // ADD
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0x5 => result = newAdc(&didOverflow, op1, op2, old_carry), // ADC
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0x6 => result = newSbc(op1, op2, old_carry), // SBC
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0x7 => result = newSbc(op2, op1, old_carry), // RSC
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0x8 => {
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// TST
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if (rd == 0xF)
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return undefinedTestBehaviour(cpu);
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result = op1 & op2;
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},
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0x9 => {
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// TEQ
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if (rd == 0xF)
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return undefinedTestBehaviour(cpu);
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result = op1 ^ op2;
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},
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0xA => {
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// CMP
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if (rd == 0xF)
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return undefinedTestBehaviour(cpu);
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result = op1 -% op2;
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},
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0xB => {
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// CMN
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if (rd == 0xF)
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return undefinedTestBehaviour(cpu);
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didOverflow = @addWithOverflow(u32, op1, op2, &result);
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},
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0xC => result = op1 | op2, // ORR
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0xD => result = op2, // MOV
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0xE => result = op1 & ~op2, // BIC
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0xF => result = ~op2, // MVN
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}
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// Write to Destination Register
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switch (kind) {
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0x8, 0x9, 0xA, 0xB => {}, // Test Operations
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else => {
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cpu.r[rd] = result;
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if (rd == 0xF) cpu.pipe.reload(u32, cpu);
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},
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}
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// Write Flags
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switch (kind) {
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0x0, 0x1, 0xC, 0xD, 0xE, 0xF => {
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// Logic Operation Flags
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if (S) {
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if (rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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}
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}
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},
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0x2, 0x3 => {
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// SUB, RSB Flags
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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if (kind == 0x2) {
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// SUB specific
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cpu.cpsr.c.write(op2 <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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} else {
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// RSB Specific
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cpu.cpsr.c.write(op1 <= op2);
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cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
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}
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if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
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}
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},
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0x4, 0x5 => {
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// ADD, ADC Flags
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
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}
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},
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0x6, 0x7 => {
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// SBC, RSC Flags
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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if (kind == 0x6) {
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// SBC specific
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const subtrahend = @as(u64, op2) -% old_carry +% 1;
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cpu.cpsr.c.write(subtrahend <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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} else {
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// RSC Specific
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const subtrahend = @as(u64, op1) -% old_carry +% 1;
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cpu.cpsr.c.write(subtrahend <= op2);
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cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
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}
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if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
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}
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},
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0x8, 0x9, 0xA, 0xB => {
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// Test Operation Flags
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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if (kind == 0xA) {
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// CMP specific
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cpu.cpsr.c.write(op2 <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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} else if (kind == 0xB) {
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// CMN specific
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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} else {
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// TEST, TEQ specific
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// Barrel Shifter should always calc CPSR C in TST
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if (!S) _ = execute(true, cpu, opcode);
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}
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},
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}
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}
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}.inner;
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}
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// pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
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// return struct {
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// fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
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// const rd = @truncate(u4, opcode >> 12 & 0xF);
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// const rn = opcode >> 16 & 0xF;
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// const old_carry = @boolToInt(cpu.cpsr.c.read());
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// // If certain conditions are met, PC is 12 ahead instead of 8
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// // TODO: What are these conditions? I can't remember
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// if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
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// const op1 = cpu.r[rn];
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// const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
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// const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
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// // Undo special condition from above
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// if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
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// switch (instrKind) {
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// 0x0 => {
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// // AND
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// const result = op1 & op2;
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// cpu.r[rd] = result;
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// setArmLogicOpFlags(S, cpu, rd, result);
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// },
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// 0x1 => {
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// // EOR
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// const result = op1 ^ op2;
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// cpu.r[rd] = result;
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// setArmLogicOpFlags(S, cpu, rd, result);
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// },
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// 0x2 => {
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// // SUB
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// cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
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// },
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// 0x3 => {
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// // RSB
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// cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
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// },
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// 0x4 => {
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// // ADD
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// cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
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// },
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// 0x5 => {
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// // ADC
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// cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
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// },
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// 0x6 => {
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// // SBC
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// cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
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// },
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// 0x7 => {
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// // RSC
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// cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
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// },
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// 0x8 => {
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// // TST
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// if (rd == 0xF)
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// return undefinedTestBehaviour(cpu);
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// const result = op1 & op2;
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// setTestOpFlags(S, cpu, opcode, result);
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// },
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// 0x9 => {
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// // TEQ
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// if (rd == 0xF)
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// return undefinedTestBehaviour(cpu);
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// const result = op1 ^ op2;
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// setTestOpFlags(S, cpu, opcode, result);
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// },
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// 0xA => {
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// // CMP
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// if (rd == 0xF)
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// return undefinedTestBehaviour(cpu);
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// cmp(cpu, op1, op2);
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// },
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// 0xB => {
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// // CMN
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// if (rd == 0xF)
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// return undefinedTestBehaviour(cpu);
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// cmn(cpu, op1, op2);
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// },
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// 0xC => {
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// // ORR
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// const result = op1 | op2;
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// cpu.r[rd] = result;
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// setArmLogicOpFlags(S, cpu, rd, result);
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// },
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// 0xD => {
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// // MOV
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// cpu.r[rd] = op2;
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// setArmLogicOpFlags(S, cpu, rd, op2);
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// },
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// 0xE => {
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// // BIC
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// const result = op1 & ~op2;
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// cpu.r[rd] = result;
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// setArmLogicOpFlags(S, cpu, rd, result);
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// },
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// 0xF => {
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// // MVN
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// const result = ~op2;
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// cpu.r[rd] = result;
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// setArmLogicOpFlags(S, cpu, rd, result);
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// },
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// }
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// if (rd == 0xF) cpu.pipe.reload(u32, cpu);
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// }
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// }.inner;
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// }
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fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
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var result: u32 = undefined;
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if (S and rd == 0xF) {
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result = sbc(false, cpu, left, right, old_carry);
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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result = sbc(S, cpu, left, right, old_carry);
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}
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return result;
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}
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fn newSbc(left: u32, right: u32, old_carry: u1) u32 {
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// TODO: Make your own version (thanks peach.bot)
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const subtrahend = @as(u64, right) -% old_carry +% 1;
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const ret = @truncate(u32, left -% subtrahend);
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return ret;
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}
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pub fn sbc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
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// TODO: Make your own version (thanks peach.bot)
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const subtrahend = @as(u64, right) -% old_carry +% 1;
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const result = @truncate(u32, left -% subtrahend);
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(subtrahend <= left);
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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}
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return result;
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}
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fn armSub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
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var result: u32 = undefined;
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if (S and rd == 0xF) {
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result = sub(false, cpu, left, right);
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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result = sub(S, cpu, left, right);
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}
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return result;
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}
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pub fn sub(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
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const result = left -% right;
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(right <= left);
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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}
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return result;
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}
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fn armAdd(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
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var result: u32 = undefined;
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if (S and rd == 0xF) {
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result = add(false, cpu, left, right);
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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result = add(S, cpu, left, right);
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}
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return result;
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}
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fn newAdd(didOverflow: *bool, left: u32, right: u32) u32 {
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var ret: u32 = undefined;
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didOverflow.* = @addWithOverflow(u32, left, right, &ret);
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return ret;
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}
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pub fn add(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
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var result: u32 = undefined;
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const didOverflow = @addWithOverflow(u32, left, right, &result);
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
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}
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return result;
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}
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fn armAdc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
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var result: u32 = undefined;
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if (S and rd == 0xF) {
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result = adc(false, cpu, left, right, old_carry);
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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result = adc(S, cpu, left, right, old_carry);
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}
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return result;
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}
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fn newAdc(didOverflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
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var ret: u32 = undefined;
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const did = @addWithOverflow(u32, left, right, &ret);
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const overflow = @addWithOverflow(u32, ret, old_carry, &ret);
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didOverflow.* = did or overflow;
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return ret;
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}
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pub fn adc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
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var result: u32 = undefined;
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const did = @addWithOverflow(u32, left, right, &result);
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const overflow = @addWithOverflow(u32, result, old_carry, &result);
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(did or overflow);
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cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
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}
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return result;
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}
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pub fn cmp(cpu: *Arm7tdmi, left: u32, right: u32) void {
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const result = left -% right;
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(right <= left);
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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}
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pub fn cmn(cpu: *Arm7tdmi, left: u32, right: u32) void {
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var result: u32 = undefined;
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const didOverflow = @addWithOverflow(u32, left, right, &result);
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
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}
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fn setArmLogicOpFlags(comptime S: bool, cpu: *Arm7tdmi, rd: u4, result: u32) void {
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if (S and rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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setLogicOpFlags(S, cpu, result);
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}
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}
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pub fn setLogicOpFlags(comptime S: bool, cpu: *Arm7tdmi, result: u32) void {
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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}
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}
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fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) void {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// Barrel Shifter should always calc CPSR C in TST
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if (!S) _ = execute(true, cpu, opcode);
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}
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fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
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@setCold(true);
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cpu.setCpsrNoFlush(cpu.spsr.raw);
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}
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