58 lines
2.0 KiB
Zig
58 lines
2.0 KiB
Zig
const std = @import("std");
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const util = @import("../../../util.zig");
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const shifter = @import("../barrel_shifter.zig");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").arm.InstrFn;
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const rotr = @import("../../../util.zig").rotr;
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pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
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const rn = opcode >> 16 & 0xF;
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const rd = opcode >> 12 & 0xF;
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var base: u32 = undefined;
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if (rn == 0xF) {
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base = cpu.fakePC();
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if (!L) base += 4; // Offset of 12
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} else {
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base = cpu.r[rn];
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}
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const offset = if (I) shifter.immShift(false, cpu, opcode) else opcode & 0xFFF;
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const modified_base = if (U) base +% offset else base -% offset;
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var address = if (P) modified_base else base;
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var result: u32 = undefined;
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if (L) {
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if (B) {
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// LDRB
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result = bus.read(u8, address);
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} else {
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// LDR
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const value = bus.read(u32, address);
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result = rotr(u32, value, 8 * (address & 0x3));
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}
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} else {
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if (B) {
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// STRB
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const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
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bus.write(u8, address, @truncate(u8, value));
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} else {
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// STR
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const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
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bus.write(u32, address, value);
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}
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}
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address = modified_base;
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if (W and P or !P) cpu.r[rn] = address;
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if (L) cpu.r[rd] = result; // This emulates the LDR rd == rn behaviour
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}
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}.inner;
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}
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