71 lines
2.5 KiB
Zig
71 lines
2.5 KiB
Zig
const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").arm.InstrFn;
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const sext = @import("../../../util.zig").sext;
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const rotr = @import("../../../util.zig").rotr;
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pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
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const rn = opcode >> 16 & 0xF;
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const rd = opcode >> 12 & 0xF;
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const rm = opcode & 0xF;
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const imm_offset_high = opcode >> 8 & 0xF;
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var base: u32 = undefined;
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if (rn == 0xF) {
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base = cpu.fakePC();
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if (!L) base += 4;
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} else {
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base = cpu.r[rn];
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}
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var offset: u32 = undefined;
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if (I) {
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offset = imm_offset_high << 4 | rm;
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} else {
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offset = cpu.r[rm];
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}
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const modified_base = if (U) base +% offset else base -% offset;
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var address = if (P) modified_base else base;
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var result: u32 = undefined;
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if (L) {
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switch (@truncate(u2, opcode >> 5)) {
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0b01 => {
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// LDRH
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const value = bus.read(u16, address);
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result = rotr(u32, value, 8 * (address & 1));
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},
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0b10 => {
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// LDRSB
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result = sext(u32, u8, bus.read(u8, address));
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},
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0b11 => {
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// LDRSH
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result = if (address & 1 == 1) blk: {
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break :blk sext(u32, u8, bus.read(u8, address));
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} else blk: {
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break :blk sext(u32, u16, bus.read(u16, address));
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};
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},
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0b00 => unreachable, // SWP
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}
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} else {
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if (opcode >> 5 & 0x01 == 0x01) {
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// STRH
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bus.write(u16, address, @truncate(u16, cpu.r[rd]));
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} else unreachable; // SWP
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}
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address = modified_base;
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if (W and P or !P) cpu.r[rn] = address;
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if (L) cpu.r[rd] = result; // // This emulates the LDR rd == rn behaviour
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}
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}.inner;
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}
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