302 lines
12 KiB
Zig
302 lines
12 KiB
Zig
const std = @import("std");
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const util = @import("../../util.zig");
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const DmaControl = @import("io.zig").DmaControl;
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const Bus = @import("../Bus.zig");
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const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
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pub const DmaTuple = std.meta.Tuple(&[_]type{ DmaController(0), DmaController(1), DmaController(2), DmaController(3) });
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const log = std.log.scoped(.DmaTransfer);
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pub fn create() DmaTuple {
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return .{ DmaController(0).init(), DmaController(1).init(), DmaController(2).init(), DmaController(3).init() };
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}
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pub fn read(comptime T: type, dma: *const DmaTuple, addr: u32) ?T {
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const byte = @truncate(u8, addr);
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return switch (T) {
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u32 => switch (byte) {
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0xB8 => @as(T, dma.*[0].cnt.raw) << 16,
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0xC4 => @as(T, dma.*[1].cnt.raw) << 16,
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0xD0 => @as(T, dma.*[2].cnt.raw) << 16,
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0xDC => @as(T, dma.*[3].cnt.raw) << 16,
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else => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
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},
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u16 => switch (byte) {
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0xBA => dma.*[0].cnt.raw,
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0xC6 => dma.*[1].cnt.raw,
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0xD2 => dma.*[2].cnt.raw,
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0xDE => dma.*[3].cnt.raw,
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else => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
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},
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u8 => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
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else => @compileError("DMA: Unsupported read width"),
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};
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}
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pub fn write(comptime T: type, dma: *DmaTuple, addr: u32, value: T) void {
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const byte = @truncate(u8, addr);
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switch (T) {
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u32 => switch (byte) {
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0xB0 => dma.*[0].setSad(value),
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0xB4 => dma.*[0].setDad(value),
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0xB8 => dma.*[0].setCnt(value),
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0xBC => dma.*[1].setSad(value),
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0xC0 => dma.*[1].setDad(value),
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0xC4 => dma.*[1].setCnt(value),
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0xC8 => dma.*[2].setSad(value),
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0xCC => dma.*[2].setDad(value),
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0xD0 => dma.*[2].setCnt(value),
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0xD4 => dma.*[3].setSad(value),
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0xD8 => dma.*[3].setDad(value),
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0xDC => dma.*[3].setCnt(value),
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else => util.io.write.undef(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
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},
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u16 => switch (byte) {
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0xB0 => dma.*[0].setSad(setU32L(dma.*[0].sad, value)),
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0xB2 => dma.*[0].setSad(setU32H(dma.*[0].sad, value)),
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0xB4 => dma.*[0].setDad(setU32L(dma.*[0].dad, value)),
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0xB6 => dma.*[0].setDad(setU32H(dma.*[0].dad, value)),
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0xB8 => dma.*[0].setCntL(value),
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0xBA => dma.*[0].setCntH(value),
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0xBC => dma.*[1].setSad(setU32L(dma.*[1].sad, value)),
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0xBE => dma.*[1].setSad(setU32H(dma.*[1].sad, value)),
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0xC0 => dma.*[1].setDad(setU32L(dma.*[1].dad, value)),
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0xC2 => dma.*[1].setDad(setU32H(dma.*[1].dad, value)),
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0xC4 => dma.*[1].setCntL(value),
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0xC6 => dma.*[1].setCntH(value),
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0xC8 => dma.*[2].setSad(setU32L(dma.*[2].sad, value)),
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0xCA => dma.*[2].setSad(setU32H(dma.*[2].sad, value)),
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0xCC => dma.*[2].setDad(setU32L(dma.*[2].dad, value)),
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0xCE => dma.*[2].setDad(setU32H(dma.*[2].dad, value)),
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0xD0 => dma.*[2].setCntL(value),
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0xD2 => dma.*[2].setCntH(value),
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0xD4 => dma.*[3].setSad(setU32L(dma.*[3].sad, value)),
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0xD6 => dma.*[3].setSad(setU32H(dma.*[3].sad, value)),
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0xD8 => dma.*[3].setDad(setU32L(dma.*[3].dad, value)),
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0xDA => dma.*[3].setDad(setU32H(dma.*[3].dad, value)),
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0xDC => dma.*[3].setCntL(value),
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0xDE => dma.*[3].setCntH(value),
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else => util.io.write.undef(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
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},
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u8 => util.io.write.undef(log, "Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
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else => @compileError("DMA: Unsupported write width"),
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}
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}
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/// Function that creates a DMAController. Determines unique DMA Controller behaiour at compile-time
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fn DmaController(comptime id: u2) type {
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return struct {
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const Self = @This();
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const sad_mask: u32 = if (id == 0) 0x07FF_FFFF else 0x0FFF_FFFF;
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const dad_mask: u32 = if (id != 3) 0x07FF_FFFF else 0x0FFF_FFFF;
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/// Write-only. The first address in a DMA transfer. (DMASAD)
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/// Note: use writeSrc instead of manipulating src_addr directly
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sad: u32,
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/// Write-only. The final address in a DMA transffer. (DMADAD)
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/// Note: Use writeDst instead of manipulatig dst_addr directly
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dad: u32,
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/// Write-only. The Word Count for the DMA Transfer (DMACNT_L)
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word_count: if (id == 3) u16 else u14,
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/// Read / Write. DMACNT_H
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/// Note: Use writeControl instead of manipulating cnt directly.
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cnt: DmaControl,
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/// Internal. Currrent Source Address
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_sad: u32,
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/// Internal. Current Destination Address
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_dad: u32,
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/// Internal. Word Count
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_word_count: if (id == 3) u16 else u14,
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// Internal. FIFO Word Count
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_fifo_word_count: u8,
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/// Some DMA Transfers are enabled during Hblank / VBlank and / or
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/// have delays. Thefore bit 15 of DMACNT isn't actually something
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/// we can use to control when we do or do not execute a step in a DMA Transfer
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in_progress: bool,
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pub fn init() Self {
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return .{
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.sad = 0,
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.dad = 0,
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.word_count = 0,
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.cnt = .{ .raw = 0x000 },
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// Internals
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._sad = 0,
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._dad = 0,
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._word_count = 0,
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._fifo_word_count = 4,
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.in_progress = false,
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};
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}
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pub fn setSad(self: *Self, addr: u32) void {
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self.sad = addr & sad_mask;
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}
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pub fn setDad(self: *Self, addr: u32) void {
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self.dad = addr & dad_mask;
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}
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pub fn setCntL(self: *Self, halfword: u16) void {
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self.word_count = @truncate(@TypeOf(self.word_count), halfword);
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}
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pub fn setCntH(self: *Self, halfword: u16) void {
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const new = DmaControl{ .raw = halfword };
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if (!self.cnt.enabled.read() and new.enabled.read()) {
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// Reload Internals on Rising Edge.
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self._sad = self.sad;
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self._dad = self.dad;
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self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
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// Only a Start Timing of 00 has a DMA Transfer immediately begin
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self.in_progress = new.start_timing.read() == 0b00;
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}
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self.cnt.raw = halfword;
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}
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pub fn setCnt(self: *Self, word: u32) void {
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self.setCntL(@truncate(u16, word));
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self.setCntH(@truncate(u16, word >> 16));
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}
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pub fn step(self: *Self, cpu: *Arm7tdmi) void {
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const is_fifo = (id == 1 or id == 2) and self.cnt.start_timing.read() == 0b11;
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const sad_adj = Self.adjustment(self.cnt.sad_adj.read());
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const dad_adj = if (is_fifo) .Fixed else Self.adjustment(self.cnt.dad_adj.read());
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const transfer_type = is_fifo or self.cnt.transfer_type.read();
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const offset: u32 = if (transfer_type) @sizeOf(u32) else @sizeOf(u16);
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const mask = if (transfer_type) ~@as(u32, 3) else ~@as(u32, 1);
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if (transfer_type) {
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cpu.bus.write(u32, self._dad & mask, cpu.bus.read(u32, self._sad & mask));
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} else {
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cpu.bus.write(u16, self._dad & mask, cpu.bus.read(u16, self._sad & mask));
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}
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switch (sad_adj) {
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.Increment => self._sad +%= offset,
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.Decrement => self._sad -%= offset,
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// TODO: Is just ignoring this ok?
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.IncrementReload => log.err("{} is a prohibited adjustment on SAD", .{sad_adj}),
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.Fixed => {},
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}
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switch (dad_adj) {
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.Increment, .IncrementReload => self._dad +%= offset,
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.Decrement => self._dad -%= offset,
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.Fixed => {},
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}
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self._word_count -= 1;
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if (self._word_count == 0) {
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if (self.cnt.irq.read()) {
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switch (id) {
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0 => cpu.bus.io.irq.dma0.set(),
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1 => cpu.bus.io.irq.dma1.set(),
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2 => cpu.bus.io.irq.dma2.set(),
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3 => cpu.bus.io.irq.dma3.set(),
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}
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cpu.handleInterrupt();
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}
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// If we're not repeating, Fire the IRQs and disable the DMA
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if (!self.cnt.repeat.read()) self.cnt.enabled.unset();
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// We want to disable our internal enabled flag regardless of repeat
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// because we only want to step A DMA that repeats during it's specific
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// timing window
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self.in_progress = false;
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}
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}
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pub fn pollBlankingDma(self: *Self, comptime kind: DmaKind) void {
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if (self.in_progress) return; // If there's an ongoing DMA Transfer, exit early
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// No ongoing DMA Transfer, We want to check if we should repeat an existing one
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// Determined by the repeat bit and whether the DMA is in the right start_timing
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switch (kind) {
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.VBlank => self.in_progress = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b01,
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.HBlank => self.in_progress = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b10,
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.Immediate, .Special => {},
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}
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// If we determined that the repeat bit is set (and now the Hblank / Vblank DMA is now in progress)
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// Reload internal word count latch
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// Reload internal DAD latch if we are in IncrementRelaod
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if (self.in_progress) {
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self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
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if (Self.adjustment(self.cnt.dad_adj.read()) == .IncrementReload) self._dad = self.dad;
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}
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}
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pub fn requestSoundDma(self: *Self, _: u32) void {
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comptime std.debug.assert(id == 1 or id == 2);
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if (self.in_progress) return; // APU must wait their turn
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// DMA May not be configured for handling DMAs
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if (self.cnt.start_timing.read() != 0b11) return;
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// We Assume the Repeat Bit is Set
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// We Assume that DAD is set to 0x0400_00A0 or 0x0400_00A4 (fifo_addr)
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// We Assume DMACNT_L is set to 4
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// FIXME: Safe to just assume whatever DAD is set to is the FIFO Address?
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// self._dad = fifo_addr;
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self.cnt.repeat.set();
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self._word_count = 4;
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self.in_progress = true;
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}
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fn adjustment(idx: u2) Adjustment {
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return std.meta.intToEnum(Adjustment, idx) catch unreachable;
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}
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};
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}
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pub fn pollBlankingDma(bus: *Bus, comptime kind: DmaKind) void {
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bus.dma[0].pollBlankingDma(kind);
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bus.dma[1].pollBlankingDma(kind);
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bus.dma[2].pollBlankingDma(kind);
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bus.dma[3].pollBlankingDma(kind);
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}
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const Adjustment = enum(u2) {
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Increment = 0,
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Decrement = 1,
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Fixed = 2,
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IncrementReload = 3,
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};
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const DmaKind = enum(u2) {
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Immediate = 0,
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HBlank,
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VBlank,
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Special,
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};
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fn setU32L(left: u32, right: u16) u32 {
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return (left & 0xFFFF_0000) | right;
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}
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fn setU32H(left: u32, right: u16) u32 {
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return (left & 0x0000_FFFF) | (@as(u32, right) << 16);
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}
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