681 lines
20 KiB
Zig
681 lines
20 KiB
Zig
const std = @import("std");
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const timer = @import("timer.zig");
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const dma = @import("dma.zig");
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const apu = @import("../apu.zig");
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const ppu = @import("../ppu.zig");
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const util = @import("../../util.zig");
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const Bit = @import("bitfield").Bit;
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const Bitfield = @import("bitfield").Bitfield;
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const Bus = @import("../Bus.zig");
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const getHalf = util.getHalf;
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const setHalf = util.setHalf;
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const log = std.log.scoped(.@"I/O");
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pub const Io = struct {
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const Self = @This();
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/// Read / Write
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ime: bool,
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ie: InterruptEnable,
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irq: InterruptRequest,
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postflg: PostFlag,
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waitcnt: WaitControl,
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haltcnt: HaltControl,
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keyinput: AtomicKeyInput,
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pub fn init() Self {
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return .{
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.ime = false,
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.ie = .{ .raw = 0x0000 },
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.irq = .{ .raw = 0x0000 },
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.keyinput = AtomicKeyInput.init(.{ .raw = 0x03FF }),
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.waitcnt = .{ .raw = 0x0000_0000 }, // Bit 15 == 0 for GBA
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.postflg = .FirstBoot,
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.haltcnt = .Execute,
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};
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}
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pub fn reset(self: *Self) void {
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self.* = Self.init();
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}
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fn setIrqs(self: *Io, word: u32) void {
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self.ie.raw = @truncate(u16, word);
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self.irq.raw &= ~@truncate(u16, word >> 16);
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}
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};
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pub fn read(bus: *const Bus, comptime T: type, address: u32) ?T {
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return switch (T) {
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u32 => switch (address) {
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// Display
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0x0400_0000...0x0400_0054 => ppu.read(T, &bus.ppu, address),
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// Sound
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0x0400_0060...0x0400_00A4 => apu.read(T, &bus.apu, address),
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// DMA Transfers
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0x0400_00B0...0x0400_00DC => dma.read(T, &bus.dma, address),
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// Timers
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0x0400_0100...0x0400_010C => timer.read(T, &bus.tim, address),
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// Serial Communication 1
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0x0400_0128 => util.io.read.todo(log, "Read {} from SIOCNT and SIOMLT_SEND", .{T}),
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// Keypad Input
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0x0400_0130 => util.io.read.todo(log, "Read {} from KEYINPUT", .{T}),
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// Serial Communication 2
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0x0400_0150 => util.io.read.todo(log, "Read {} from JOY_RECV", .{T}),
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// Interrupts
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0x0400_0200 => @as(u32, bus.io.irq.raw) << 16 | bus.io.ie.raw,
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0x0400_0204 => bus.io.waitcnt.raw,
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0x0400_0208 => @boolToInt(bus.io.ime),
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0x0400_0300 => @enumToInt(bus.io.postflg),
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else => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, address }),
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},
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u16 => switch (address) {
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// Display
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0x0400_0000...0x0400_0054 => ppu.read(T, &bus.ppu, address),
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// Sound
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0x0400_0060...0x0400_00A6 => apu.read(T, &bus.apu, address),
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// DMA Transfers
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0x0400_00B0...0x0400_00DE => dma.read(T, &bus.dma, address),
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// Timers
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0x0400_0100...0x0400_010E => timer.read(T, &bus.tim, address),
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// Serial Communication 1
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0x0400_0128 => util.io.read.todo(log, "Read {} from SIOCNT", .{T}),
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// Keypad Input
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0x0400_0130 => bus.io.keyinput.load(.Monotonic),
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// Serial Communication 2
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0x0400_0134 => util.io.read.todo(log, "Read {} from RCNT", .{T}),
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0x0400_0136 => 0x0000,
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0x0400_0142 => 0x0000,
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0x0400_015A => 0x0000,
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// Interrupts
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0x0400_0200 => bus.io.ie.raw,
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0x0400_0202 => bus.io.irq.raw,
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0x0400_0204 => bus.io.waitcnt.raw,
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0x0400_0206 => 0x0000,
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0x0400_0208 => @boolToInt(bus.io.ime),
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0x0400_020A => 0x0000,
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0x0400_0300 => @enumToInt(bus.io.postflg),
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0x0400_0302 => 0x0000,
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else => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, address }),
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},
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u8 => return switch (address) {
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// Display
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0x0400_0000...0x0400_0055 => ppu.read(T, &bus.ppu, address),
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// Sound
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0x0400_0060...0x0400_00A7 => apu.read(T, &bus.apu, address),
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// DMA Transfers
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0x0400_00B0...0x0400_00DF => dma.read(T, &bus.dma, address),
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// Timers
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0x0400_0100...0x0400_010F => timer.read(T, &bus.tim, address),
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// Serial Communication 1
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0x0400_0128 => util.io.read.todo(log, "Read {} from SIOCNT_L", .{T}),
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// Keypad Input
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0x0400_0130 => util.io.read.todo(log, "read {} from KEYINPUT_L", .{T}),
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// Serial Communication 2
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0x0400_0135 => util.io.read.todo(log, "Read {} from RCNT_H", .{T}),
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0x0400_0136, 0x0400_0137 => 0x00,
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0x0400_0142, 0x0400_0143 => 0x00,
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0x0400_015A, 0x0400_015B => 0x00,
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// Interrupts
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0x0400_0200, 0x0400_0201 => @truncate(T, bus.io.ie.raw >> getHalf(@truncate(u8, address))),
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0x0400_0202, 0x0400_0203 => @truncate(T, bus.io.irq.raw >> getHalf(@truncate(u8, address))),
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0x0400_0204, 0x0400_0205 => @truncate(T, bus.io.waitcnt.raw >> getHalf(@truncate(u8, address))),
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0x0400_0206, 0x0400_0207 => 0x00,
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0x0400_0208, 0x0400_0209 => @truncate(T, @as(u16, @boolToInt(bus.io.ime)) >> getHalf(@truncate(u8, address))),
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0x0400_020A, 0x0400_020B => 0x00,
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0x0400_0300 => @enumToInt(bus.io.postflg),
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0x0400_0301 => null,
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0x0400_0302, 0x0400_0303 => 0x00,
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else => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, address }),
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},
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else => @compileError("I/O: Unsupported read width"),
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};
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}
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pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
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return switch (T) {
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u32 => switch (address) {
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// Display
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0x0400_0000...0x0400_0054 => ppu.write(T, &bus.ppu, address, value),
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0x0400_0058...0x0400_005C => {}, // Unused
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// Sound
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0x0400_0060...0x0400_00A4 => apu.write(T, &bus.apu, address, value),
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0x0400_00A8, 0x0400_00AC => {}, // Unused
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// DMA Transfers
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0x0400_00B0...0x0400_00DC => dma.write(T, &bus.dma, address, value),
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0x0400_00E0...0x0400_00FC => {}, // Unused
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// Timers
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0x0400_0100...0x0400_010C => timer.write(T, &bus.tim, address, value),
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0x0400_0110...0x0400_011C => {}, // Unused
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// Serial Communication 1
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0x0400_0120 => log.debug("Wrote 0x{X:0>8} to SIODATA32/(SIOMULTI0 and SIOMULTI1)", .{value}),
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0x0400_0124 => log.debug("Wrote 0x{X:0>8} to SIOMULTI2 and SIOMULTI3", .{value}),
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0x0400_0128 => log.debug("Wrote 0x{X:0>8} to SIOCNT and SIOMLT_SEND/SIODATA8", .{value}),
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0x0400_012C => {}, // Unused
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// Keypad Input
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0x0400_0130 => log.debug("Wrote 0x{X:0>8} to KEYINPUT and KEYCNT", .{value}),
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0x0400_0134 => log.debug("Wrote 0x{X:0>8} to RCNT and IR", .{value}),
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0x0400_0138, 0x0400_013C => {}, // Unused
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// Serial Communication 2
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0x0400_0140 => log.debug("Wrote 0x{X:0>8} to JOYCNT", .{value}),
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0x0400_0150 => log.debug("Wrote 0x{X:0>8} to JOY_RECV", .{value}),
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0x0400_0154 => log.debug("Wrote 0x{X:0>8} to JOY_TRANS", .{value}),
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0x0400_0158 => log.debug("Wrote 0x{X:0>8} to JOYSTAT (?)", .{value}),
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0x0400_0144...0x0400_014C, 0x0400_015C => {}, // Unused
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0x0400_0160...0x0400_01FC => {},
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// Interrupts
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0x0400_0200 => bus.io.setIrqs(value),
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0x0400_0204 => bus.io.waitcnt.set(@truncate(u16, value)),
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0x0400_0208 => bus.io.ime = value & 1 == 1,
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0x0400_0300 => {
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bus.io.postflg = @intToEnum(PostFlag, value & 1);
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bus.io.haltcnt = if (value >> 15 & 1 == 0) .Halt else @panic("TODO: Implement STOP");
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},
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else => util.io.write.undef(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, address }),
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},
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u16 => switch (address) {
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// Display
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0x0400_0000...0x0400_0054 => ppu.write(T, &bus.ppu, address, value),
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0x0400_0056 => {}, // Not used
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// Sound
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0x0400_0060...0x0400_00A6 => apu.write(T, &bus.apu, address, value),
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// Dma Transfers
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0x0400_00B0...0x0400_00DE => dma.write(T, &bus.dma, address, value),
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// Timers
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0x0400_0100...0x0400_010E => timer.write(T, &bus.tim, address, value),
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0x0400_0114 => {},
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0x0400_0110 => {}, // Not Used,
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// Serial Communication 1
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0x0400_0120 => log.debug("Wrote 0x{X:0>4} to SIOMULTI0", .{value}),
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0x0400_0122 => log.debug("Wrote 0x{X:0>4} to SIOMULTI1", .{value}),
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0x0400_0124 => log.debug("Wrote 0x{X:0>4} to SIOMULTI2", .{value}),
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0x0400_0126 => log.debug("Wrote 0x{X:0>4} to SIOMULTI3", .{value}),
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0x0400_0128 => log.debug("Wrote 0x{X:0>4} to SIOCNT", .{value}),
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0x0400_012A => log.debug("Wrote 0x{X:0>4} to SIOMLT_SEND", .{value}),
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// Keypad Input
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0x0400_0130 => log.debug("Wrote 0x{X:0>4} to KEYINPUT. Ignored", .{value}),
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0x0400_0132 => log.debug("Wrote 0x{X:0>4} to KEYCNT", .{value}),
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// Serial Communication 2
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0x0400_0134 => log.debug("Wrote 0x{X:0>4} to RCNT", .{value}),
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0x0400_0140 => log.debug("Wrote 0x{X:0>4} to JOYCNT", .{value}),
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0x0400_0158 => log.debug("Wrote 0x{X:0>4} to JOYSTAT", .{value}),
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0x0400_0142, 0x0400_015A => {}, // Not Used
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// Interrupts
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0x0400_0200 => bus.io.ie.raw = value,
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0x0400_0202 => bus.io.irq.raw &= ~value,
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0x0400_0204 => bus.io.waitcnt.set(value),
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0x0400_0206 => {},
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0x0400_0208 => bus.io.ime = value & 1 == 1,
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0x0400_020A => {},
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0x0400_0300 => {
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bus.io.postflg = @intToEnum(PostFlag, value & 1);
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bus.io.haltcnt = if (value >> 15 & 1 == 0) .Halt else @panic("TODO: Implement STOP");
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},
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else => util.io.write.undef(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, address }),
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},
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u8 => switch (address) {
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// Display
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0x0400_0000...0x0400_0055 => ppu.write(T, &bus.ppu, address, value),
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// Sound
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0x0400_0060...0x0400_00A7 => apu.write(T, &bus.apu, address, value),
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// Dma Transfers
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0x0400_00B0...0x0400_00DF => dma.write(T, &bus.dma, address, value),
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// Timers
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0x0400_0100...0x0400_010F => timer.write(T, &bus.tim, address, value),
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// Serial Communication 1
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0x0400_0120 => log.debug("Wrote 0x{X:0>2} to SIODATA32_L_L", .{value}),
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0x0400_0128 => log.debug("Wrote 0x{X:0>2} to SIOCNT_L", .{value}),
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// Serial Communication 2
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0x0400_0135 => log.debug("Wrote 0x{X:0>2} to RCNT_H", .{value}),
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0x0400_0140 => log.debug("Wrote 0x{X:0>2} to JOYCNT_L", .{value}),
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// Interrupts
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0x0400_0200, 0x0400_0201 => bus.io.ie.raw = setHalf(u16, bus.io.ie.raw, @truncate(u8, address), value),
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0x0400_0202 => bus.io.irq.raw &= ~@as(u16, value),
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0x0400_0203 => bus.io.irq.raw &= ~@as(u16, value) << 8, // TODO: Is this good?
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0x0400_0204, 0x0400_0205 => bus.io.waitcnt.set(setHalf(u16, @truncate(u16, bus.io.waitcnt.raw), @truncate(u8, address), value)),
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0x0400_0206, 0x0400_0207 => {},
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0x0400_0208 => bus.io.ime = value & 1 == 1,
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0x0400_0209 => {},
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0x0400_020A, 0x0400_020B => {},
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0x0400_0300 => bus.io.postflg = @intToEnum(PostFlag, value & 1),
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0x0400_0301 => bus.io.haltcnt = if (value >> 7 & 1 == 0) .Halt else std.debug.panic("TODO: Implement STOP", .{}),
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0x0400_0410 => log.debug("Wrote 0x{X:0>2} to the common yet undocumented 0x{X:0>8}", .{ value, address }),
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else => util.io.write.undef(log, "Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, address }),
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},
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else => @compileError("I/O: Unsupported write width"),
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};
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}
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/// Read / Write
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pub const PostFlag = enum(u1) {
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FirstBoot = 0,
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FurtherBoots = 1,
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};
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/// Write Only
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pub const HaltControl = enum {
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Halt,
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Stop,
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Execute,
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};
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/// Read / Write
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pub const DisplayControl = extern union {
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bg_mode: Bitfield(u16, 0, 3),
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frame_select: Bit(u16, 4),
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hblank_interval_free: Bit(u16, 5),
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obj_mapping: Bit(u16, 6),
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forced_blank: Bit(u16, 7),
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bg_enable: Bitfield(u16, 8, 4),
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obj_enable: Bit(u16, 12),
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win_enable: Bitfield(u16, 13, 2),
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obj_win_enable: Bit(u16, 15),
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raw: u16,
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};
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/// Read / Write
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pub const DisplayStatus = extern union {
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/// read-only
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vblank: Bit(u16, 0),
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/// read-only
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hblank: Bit(u16, 1),
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// read-only
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coincidence: Bit(u16, 2),
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vblank_irq: Bit(u16, 3),
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hblank_irq: Bit(u16, 4),
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vcount_irq: Bit(u16, 5),
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vcount_trigger: Bitfield(u16, 8, 8),
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raw: u16,
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pub fn set(self: *DisplayStatus, value: u16) void {
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const mask: u16 = 0x00C7; // set bits are read-only
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self.raw = (self.raw & mask) | (value & ~mask);
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}
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};
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/// Read Only
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pub const VCount = extern union {
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scanline: Bitfield(u16, 0, 8),
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raw: u16,
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};
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/// Read / Write
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const InterruptEnable = extern union {
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vblank: Bit(u16, 0),
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hblank: Bit(u16, 1),
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coincidence: Bit(u16, 2),
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tim0: Bit(u16, 3),
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tim1: Bit(u16, 4),
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tim2: Bit(u16, 5),
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tim3: Bit(u16, 6),
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serial: Bit(u16, 7),
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dma0: Bit(u16, 8),
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dma1: Bit(u16, 9),
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dma2: Bit(u16, 10),
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dma3: Bit(u16, 11),
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keypad: Bit(u16, 12),
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game_pak: Bit(u16, 13),
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raw: u16,
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};
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/// Read Only
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/// 0 = Pressed, 1 = Released
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pub const KeyInput = extern union {
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a: Bit(u16, 0),
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b: Bit(u16, 1),
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select: Bit(u16, 2),
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start: Bit(u16, 3),
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right: Bit(u16, 4),
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left: Bit(u16, 5),
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up: Bit(u16, 6),
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down: Bit(u16, 7),
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shoulder_r: Bit(u16, 8),
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shoulder_l: Bit(u16, 9),
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raw: u16,
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};
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const AtomicKeyInput = struct {
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const Self = @This();
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const Ordering = std.atomic.Ordering;
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inner: KeyInput,
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pub fn init(value: KeyInput) Self {
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return .{ .inner = value };
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}
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pub inline fn load(self: *const Self, comptime ordering: Ordering) u16 {
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return switch (ordering) {
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.AcqRel, .Release => @compileError("not supported for atomic loads"),
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else => @atomicLoad(u16, &self.inner.raw, ordering),
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};
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}
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pub inline fn fetchOr(self: *Self, value: u16, comptime ordering: Ordering) void {
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_ = @atomicRmw(u16, &self.inner.raw, .Or, value, ordering);
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}
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pub inline fn fetchAnd(self: *Self, value: u16, comptime ordering: Ordering) void {
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_ = @atomicRmw(u16, &self.inner.raw, .And, value, ordering);
|
|
}
|
|
};
|
|
|
|
// Read / Write
|
|
pub const BackgroundControl = extern union {
|
|
priority: Bitfield(u16, 0, 2),
|
|
char_base: Bitfield(u16, 2, 2),
|
|
mosaic_enable: Bit(u16, 6),
|
|
colour_mode: Bit(u16, 7),
|
|
screen_base: Bitfield(u16, 8, 5),
|
|
display_overflow: Bit(u16, 13),
|
|
size: Bitfield(u16, 14, 2),
|
|
raw: u16,
|
|
};
|
|
|
|
/// Write Only
|
|
pub const BackgroundOffset = extern union {
|
|
offset: Bitfield(u16, 0, 9),
|
|
raw: u16,
|
|
};
|
|
|
|
/// Read / Write
|
|
pub const BldCnt = extern union {
|
|
/// BLDCNT{0} is BG0 A
|
|
/// BLDCNT{4} is OBJ A
|
|
/// BLDCNT{5} is BD A
|
|
layer_a: Bitfield(u16, 0, 6),
|
|
mode: Bitfield(u16, 6, 2),
|
|
|
|
/// BLDCNT{8} is BG0 B
|
|
/// BLDCNT{12} is OBJ B
|
|
/// BLDCNT{13} is BD B
|
|
layer_b: Bitfield(u16, 8, 6),
|
|
raw: u16,
|
|
};
|
|
|
|
/// Read-only?
|
|
/// Alpha Blending Coefficients
|
|
pub const BldAlpha = extern union {
|
|
eva: Bitfield(u16, 0, 5),
|
|
evb: Bitfield(u16, 8, 5),
|
|
raw: u16,
|
|
};
|
|
|
|
/// Write-only?
|
|
/// Brightness COefficients
|
|
pub const BldY = extern union {
|
|
evy: Bitfield(u16, 0, 5),
|
|
raw: u16,
|
|
};
|
|
|
|
const u8WriteKind = enum { Hi, Lo };
|
|
|
|
/// Write-only
|
|
pub const WinH = extern union {
|
|
x2: Bitfield(u16, 0, 8),
|
|
x1: Bitfield(u16, 8, 8),
|
|
raw: u16,
|
|
};
|
|
|
|
/// Write-only
|
|
pub const WinV = extern union {
|
|
const Self = @This();
|
|
|
|
y2: Bitfield(u16, 0, 8),
|
|
y1: Bitfield(u16, 8, 8),
|
|
raw: u16,
|
|
};
|
|
|
|
pub const WinIn = extern union {
|
|
w0_bg: Bitfield(u16, 0, 4),
|
|
w0_obj: Bit(u16, 4),
|
|
w0_bld: Bit(u16, 5),
|
|
w1_bg: Bitfield(u16, 8, 4),
|
|
w1_obj: Bit(u16, 12),
|
|
w1_bld: Bit(u16, 13),
|
|
raw: u16,
|
|
};
|
|
|
|
pub const WinOut = extern union {
|
|
out_bg: Bitfield(u16, 0, 4),
|
|
out_obj: Bit(u16, 4),
|
|
out_bld: Bit(u16, 5),
|
|
obj_bg: Bitfield(u16, 8, 4),
|
|
obj_obj: Bit(u16, 12),
|
|
obj_bld: Bit(u16, 13),
|
|
raw: u16,
|
|
};
|
|
|
|
/// Read / Write
|
|
const InterruptRequest = extern union {
|
|
vblank: Bit(u16, 0),
|
|
hblank: Bit(u16, 1),
|
|
coincidence: Bit(u16, 2),
|
|
tim0: Bit(u16, 3),
|
|
tim1: Bit(u16, 4),
|
|
tim2: Bit(u16, 5),
|
|
tim3: Bit(u16, 6),
|
|
serial: Bit(u16, 7),
|
|
dma0: Bit(u16, 8),
|
|
dma1: Bit(u16, 9),
|
|
dma2: Bit(u16, 10),
|
|
dma3: Bit(u16, 11),
|
|
keypad: Bit(u16, 12),
|
|
game_pak: Bit(u16, 13),
|
|
raw: u16,
|
|
};
|
|
|
|
/// Read / Write
|
|
pub const DmaControl = extern union {
|
|
dad_adj: Bitfield(u16, 5, 2),
|
|
sad_adj: Bitfield(u16, 7, 2),
|
|
repeat: Bit(u16, 9),
|
|
transfer_type: Bit(u16, 10),
|
|
pak_drq: Bit(u16, 11),
|
|
start_timing: Bitfield(u16, 12, 2),
|
|
irq: Bit(u16, 14),
|
|
enabled: Bit(u16, 15),
|
|
raw: u16,
|
|
};
|
|
|
|
/// Read / Write
|
|
pub const TimerControl = extern union {
|
|
frequency: Bitfield(u16, 0, 2),
|
|
cascade: Bit(u16, 2),
|
|
irq: Bit(u16, 6),
|
|
enabled: Bit(u16, 7),
|
|
raw: u16,
|
|
};
|
|
|
|
/// Read / Write
|
|
/// NR10
|
|
pub const Sweep = extern union {
|
|
shift: Bitfield(u8, 0, 3),
|
|
direction: Bit(u8, 3),
|
|
period: Bitfield(u8, 4, 3),
|
|
raw: u8,
|
|
};
|
|
|
|
/// Read / Write
|
|
/// This represents the Duty / Len
|
|
/// NRx1
|
|
pub const Duty = extern union {
|
|
/// Write-only
|
|
/// Only used when bit 6 is set
|
|
length: Bitfield(u16, 0, 6),
|
|
pattern: Bitfield(u16, 6, 2),
|
|
raw: u8,
|
|
};
|
|
|
|
/// Read / Write
|
|
/// NRx2
|
|
pub const Envelope = extern union {
|
|
period: Bitfield(u8, 0, 3),
|
|
direction: Bit(u8, 3),
|
|
init_vol: Bitfield(u8, 4, 4),
|
|
raw: u8,
|
|
};
|
|
|
|
/// Read / Write
|
|
/// NRx3, NRx4
|
|
pub const Frequency = extern union {
|
|
/// Write-only
|
|
frequency: Bitfield(u16, 0, 11),
|
|
length_enable: Bit(u16, 14),
|
|
/// Write-only
|
|
trigger: Bit(u16, 15),
|
|
|
|
raw: u16,
|
|
};
|
|
|
|
/// Read / Write
|
|
/// NR30
|
|
pub const WaveSelect = extern union {
|
|
dimension: Bit(u8, 5),
|
|
bank: Bit(u8, 6),
|
|
enabled: Bit(u8, 7),
|
|
raw: u8,
|
|
};
|
|
|
|
/// Read / Write
|
|
/// NR32
|
|
pub const WaveVolume = extern union {
|
|
kind: Bitfield(u8, 5, 2),
|
|
force: Bit(u8, 7),
|
|
raw: u8,
|
|
};
|
|
|
|
/// Read / Write
|
|
/// NR43
|
|
pub const PolyCounter = extern union {
|
|
div_ratio: Bitfield(u8, 0, 3),
|
|
width: Bit(u8, 3),
|
|
shift: Bitfield(u8, 4, 4),
|
|
raw: u8,
|
|
};
|
|
|
|
/// Read / Write
|
|
/// NR44
|
|
pub const NoiseControl = extern union {
|
|
length_enable: Bit(u8, 6),
|
|
trigger: Bit(u8, 7),
|
|
raw: u8,
|
|
};
|
|
|
|
/// Read / Write
|
|
pub const ChannelVolumeControl = extern union {
|
|
right_vol: Bitfield(u16, 0, 3),
|
|
left_vol: Bitfield(u16, 4, 3),
|
|
ch_right: Bitfield(u16, 8, 4),
|
|
ch_left: Bitfield(u16, 12, 4),
|
|
raw: u16,
|
|
};
|
|
|
|
/// Read / Write
|
|
pub const DmaSoundControl = extern union {
|
|
ch_vol: Bitfield(u16, 0, 2),
|
|
chA_vol: Bit(u16, 2),
|
|
chB_vol: Bit(u16, 3),
|
|
|
|
chA_right: Bit(u16, 8),
|
|
chA_left: Bit(u16, 9),
|
|
chA_timer: Bit(u16, 10),
|
|
/// Write only?
|
|
chA_reset: Bit(u16, 11),
|
|
|
|
chB_right: Bit(u16, 12),
|
|
chB_left: Bit(u16, 13),
|
|
chB_timer: Bit(u16, 14),
|
|
/// Write only?
|
|
chB_reset: Bit(u16, 15),
|
|
raw: u16,
|
|
};
|
|
|
|
/// Read / Write
|
|
pub const SoundControl = extern union {
|
|
/// Read-only
|
|
ch1_enable: Bit(u8, 0),
|
|
/// Read-only
|
|
ch2_enable: Bit(u8, 1),
|
|
/// Read-only
|
|
ch3_enable: Bit(u8, 2),
|
|
/// Read-only
|
|
ch4_enable: Bit(u8, 3),
|
|
apu_enable: Bit(u8, 7),
|
|
raw: u8,
|
|
};
|
|
|
|
/// Read / Write
|
|
pub const SoundBias = extern union {
|
|
level: Bitfield(u16, 1, 9),
|
|
sampling_cycle: Bitfield(u16, 14, 2),
|
|
raw: u16,
|
|
};
|
|
|
|
/// Read / Write
|
|
pub const WaitControl = extern union {
|
|
sram_cnt: Bitfield(u16, 0, 2),
|
|
s0_first: Bitfield(u16, 2, 2),
|
|
s0_second: Bit(u16, 4),
|
|
s1_first: Bitfield(u16, 5, 2),
|
|
s1_second: Bit(u16, 7),
|
|
s2_first: Bitfield(u16, 8, 2),
|
|
s2_second: Bit(u16, 10),
|
|
phi_out: Bitfield(u16, 11, 2),
|
|
|
|
prefetch_enable: Bit(u16, 14),
|
|
pak_kind: Bit(u16, 15),
|
|
raw: u16,
|
|
|
|
pub fn set(self: *WaitControl, value: u16) void {
|
|
const mask: u16 = 0x8000; // set bits are read-only
|
|
self.raw = (self.raw & mask) | (value & ~mask);
|
|
}
|
|
};
|