72 lines
2.6 KiB
Zig
72 lines
2.6 KiB
Zig
const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").ArmInstrFn;
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pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
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const r15_present = opcode >> 15 & 1 == 1;
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const rn = opcode >> 16 & 0xF;
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const base = cpu.r[rn];
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const in_list = opcode >> @truncate(u4, rn) & 1 == 1;
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var address: u32 = base;
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if (U) {
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// Increment
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var i: u5 = 0;
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while (i < 0x10) : (i += 1) {
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if (opcode >> i & 1 == 1) {
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if (P) address += 4;
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transfer(cpu, bus, r15_present, i, address);
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if (!P) address += 4;
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}
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}
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} else {
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// Decrement
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var i: u5 = 0x10;
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while (i > 0) : (i -= 1) {
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const j = i - 1;
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if (opcode >> j & 1 == 1) {
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if (P) address -= 4;
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transfer(cpu, bus, r15_present, j, address);
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if (!P) address -= 4;
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}
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}
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}
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if (W) {
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if (!L or (L and !in_list)) {
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cpu.r[rn] = address;
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}
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}
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}
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fn transfer(cpu: *Arm7tdmi, bus: *Bus, r15_present: bool, i: u5, address: u32) void {
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if (L) {
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if (S and !r15_present) {
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// Always Transfer User mode Registers
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cpu.setUserModeRegister(i, bus.read32(address));
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} else {
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const value = bus.read32(address);
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cpu.r[i] = if (i == 0xF) value & 0xFFFF_FFFC else value;
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if (S and i == 0xF) cpu.setCpsr(cpu.spsr.raw);
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}
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} else {
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if (S) {
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// Always Transfer User mode Registers
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// This happens regardless if r15 is in the list
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const value = cpu.getUserModeRegister(i);
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bus.write32(address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
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} else {
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bus.write32(address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
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}
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}
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}
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}.inner;
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}
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