682 lines
25 KiB
Zig
682 lines
25 KiB
Zig
const std = @import("std");
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const util = @import("util.zig");
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const Bus = @import("Bus.zig");
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const Bit = @import("bitfield").Bit;
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const Bitfield = @import("bitfield").Bitfield;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const FilePaths = @import("util.zig").FilePaths;
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const Allocator = std.mem.Allocator;
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const File = std.fs.File;
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// ARM Instruction Groups
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const dataProcessing = @import("cpu/arm/data_processing.zig").dataProcessing;
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const psrTransfer = @import("cpu/arm/psr_transfer.zig").psrTransfer;
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const singleDataTransfer = @import("cpu/arm/single_data_transfer.zig").singleDataTransfer;
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const halfAndSignedDataTransfer = @import("cpu/arm/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
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const blockDataTransfer = @import("cpu/arm/block_data_transfer.zig").blockDataTransfer;
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const branch = @import("cpu/arm/branch.zig").branch;
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const branchAndExchange = @import("cpu/arm/branch.zig").branchAndExchange;
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const armSoftwareInterrupt = @import("cpu/arm/software_interrupt.zig").armSoftwareInterrupt;
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const singleDataSwap = @import("cpu/arm/single_data_swap.zig").singleDataSwap;
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const multiply = @import("cpu/arm/multiply.zig").multiply;
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const multiplyLong = @import("cpu/arm/multiply.zig").multiplyLong;
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// THUMB Instruction Groups
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const format1 = @import("cpu/thumb/data_processing.zig").format1;
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const format2 = @import("cpu/thumb/data_processing.zig").format2;
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const format3 = @import("cpu/thumb/data_processing.zig").format3;
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const format12 = @import("cpu/thumb/data_processing.zig").format12;
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const format13 = @import("cpu/thumb/data_processing.zig").format13;
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const format4 = @import("cpu/thumb/alu.zig").format4;
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const format5 = @import("cpu/thumb/processing_branch.zig").format5;
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const format6 = @import("cpu/thumb/data_transfer.zig").format6;
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const format78 = @import("cpu/thumb/data_transfer.zig").format78;
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const format9 = @import("cpu/thumb/data_transfer.zig").format9;
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const format10 = @import("cpu/thumb/data_transfer.zig").format10;
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const format11 = @import("cpu/thumb/data_transfer.zig").format11;
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const format14 = @import("cpu/thumb/block_data_transfer.zig").format14;
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const format15 = @import("cpu/thumb/block_data_transfer.zig").format15;
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const format16 = @import("cpu/thumb/branch.zig").format16;
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const format18 = @import("cpu/thumb/branch.zig").format18;
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const format19 = @import("cpu/thumb/branch.zig").format19;
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const thumbSoftwareInterrupt = @import("cpu/thumb/software_interrupt.zig").thumbSoftwareInterrupt;
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pub const ArmInstrFn = fn (*Arm7tdmi, *Bus, u32) void;
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pub const ThumbInstrFn = fn (*Arm7tdmi, *Bus, u16) void;
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const arm_lut: [0x1000]ArmInstrFn = armPopulate();
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const thumb_lut: [0x400]ThumbInstrFn = thumbPopulate();
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const enable_logging = @import("main.zig").enable_logging;
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const log = std.log.scoped(.Arm7Tdmi);
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pub const Arm7tdmi = struct {
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const Self = @This();
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r: [16]u32,
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sched: *Scheduler,
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bus: Bus,
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cpsr: PSR,
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spsr: PSR,
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/// Storage for R8_fiq -> R12_fiq and their normal counterparts
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/// e.g [r[0 + 8], fiq_r[0 + 8], r[1 + 8], fiq_r[1 + 8]...]
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banked_fiq: [2 * 5]u32,
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/// Storage for r13_<mode>, r14_<mode>
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/// e.g. [r13, r14, r13_svc, r14_svc]
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banked_r: [2 * 6]u32,
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banked_spsr: [5]PSR,
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log_file: ?*const File,
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log_buf: [0x100]u8,
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binary_log: bool,
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pub fn init(alloc: Allocator, sched: *Scheduler, paths: FilePaths) !Self {
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return Self{
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.r = [_]u32{0x00} ** 16,
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.sched = sched,
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.bus = try Bus.init(alloc, sched, paths),
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.cpsr = .{ .raw = 0x0000_001F },
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.spsr = .{ .raw = 0x0000_0000 },
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.banked_fiq = [_]u32{0x00} ** 10,
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.banked_r = [_]u32{0x00} ** 12,
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.banked_spsr = [_]PSR{.{ .raw = 0x0000_0000 }} ** 5,
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.log_file = null,
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.log_buf = undefined,
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.binary_log = false,
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};
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}
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pub fn deinit(self: Self) void {
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self.bus.deinit();
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}
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pub fn useLogger(self: *Self, file: *const File, is_binary: bool) void {
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self.log_file = file;
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self.binary_log = is_binary;
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}
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inline fn bankedIdx(mode: Mode, kind: BankedKind) usize {
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const idx: usize = switch (mode) {
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.User, .System => 0,
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.Supervisor => 1,
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.Abort => 2,
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.Undefined => 3,
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.Irq => 4,
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.Fiq => 5,
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};
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return (idx * 2) + if (kind == .R14) @as(usize, 1) else 0;
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}
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inline fn bankedSpsrIndex(mode: Mode) usize {
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return switch (mode) {
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.Supervisor => 0,
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.Abort => 1,
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.Undefined => 2,
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.Irq => 3,
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.Fiq => 4,
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else => std.debug.panic("[CPU/Mode] {} does not have a SPSR Register", .{mode}),
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};
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}
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inline fn bankedFiqIdx(i: usize, mode: Mode) usize {
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return (i * 2) + if (mode == .Fiq) @as(usize, 1) else 0;
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}
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pub inline fn hasSPSR(self: *const Self) bool {
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const mode = getModeChecked(self, self.cpsr.mode.read());
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return switch (mode) {
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.System, .User => false,
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else => true,
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};
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}
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pub inline fn isPrivileged(self: *const Self) bool {
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const mode = getModeChecked(self, self.cpsr.mode.read());
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return switch (mode) {
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.User => false,
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else => true,
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};
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}
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pub fn setCpsr(self: *Self, value: u32) void {
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if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
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self.cpsr.raw = value;
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}
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fn changeModeFromIdx(self: *Self, next: u5) void {
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self.changeMode(getModeChecked(self, next));
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}
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pub fn setUserModeRegister(self: *Self, idx: usize, value: u32) void {
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const current = getModeChecked(self, self.cpsr.mode.read());
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switch (idx) {
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8...12 => {
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if (current == .Fiq) {
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self.banked_fiq[bankedFiqIdx(idx - 8, .User)] = value;
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} else self.r[idx] = value;
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},
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13, 14 => switch (current) {
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.User, .System => self.r[idx] = value,
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else => {
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const kind = std.meta.intToEnum(BankedKind, idx - 13) catch unreachable;
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self.banked_r[bankedIdx(.User, kind)] = value;
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},
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},
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else => self.r[idx] = value, // R0 -> R7 and R15
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}
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}
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pub fn getUserModeRegister(self: *Self, idx: usize) u32 {
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const current = getModeChecked(self, self.cpsr.mode.read());
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return switch (idx) {
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8...12 => if (current == .Fiq) self.banked_fiq[bankedFiqIdx(idx - 8, .User)] else self.r[idx],
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13, 14 => switch (current) {
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.User, .System => self.r[idx],
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else => blk: {
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const kind = std.meta.intToEnum(BankedKind, idx - 13) catch unreachable;
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break :blk self.banked_r[bankedIdx(.User, kind)];
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},
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},
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else => self.r[idx], // R0 -> R7 and R15
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};
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}
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pub fn changeMode(self: *Self, next: Mode) void {
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const now = getModeChecked(self, self.cpsr.mode.read());
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// Bank R8 -> r12
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var i: usize = 0;
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while (i < 5) : (i += 1) {
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self.banked_fiq[bankedFiqIdx(i, now)] = self.r[8 + i];
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}
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// Bank r13, r14, SPSR
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switch (now) {
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.User, .System => {
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self.banked_r[bankedIdx(now, .R13)] = self.r[13];
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self.banked_r[bankedIdx(now, .R14)] = self.r[14];
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},
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else => {
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self.banked_r[bankedIdx(now, .R13)] = self.r[13];
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self.banked_r[bankedIdx(now, .R14)] = self.r[14];
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self.banked_spsr[bankedSpsrIndex(now)] = self.spsr;
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},
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}
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// Grab R8 -> R12
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i = 0;
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while (i < 5) : (i += 1) {
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self.r[8 + i] = self.banked_fiq[bankedFiqIdx(i, next)];
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}
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// Grab r13, r14, SPSR
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switch (next) {
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.User, .System => {
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self.r[13] = self.banked_r[bankedIdx(next, .R13)];
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self.r[14] = self.banked_r[bankedIdx(next, .R14)];
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},
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else => {
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self.r[13] = self.banked_r[bankedIdx(next, .R13)];
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self.r[14] = self.banked_r[bankedIdx(next, .R14)];
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self.spsr = self.banked_spsr[bankedSpsrIndex(next)];
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},
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}
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self.cpsr.mode.write(@enumToInt(next));
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}
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pub fn fastBoot(self: *Self) void {
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self.r = std.mem.zeroes([16]u32);
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self.r[0] = 0x08000000;
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self.r[1] = 0x000000EA;
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self.r[13] = 0x0300_7F00;
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self.r[15] = 0x0800_0000;
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self.banked_r[bankedIdx(.Irq, .R13)] = 0x0300_7FA0;
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self.banked_r[bankedIdx(.Supervisor, .R13)] = 0x0300_7FE0;
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self.cpsr.raw = 0x6000001F;
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}
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pub fn step(self: *Self) void {
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if (self.cpsr.t.read()) {
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const opcode = self.fetch(u16);
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if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
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thumb_lut[thumbIdx(opcode)](self, &self.bus, opcode);
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} else {
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const opcode = self.fetch(u32);
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if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
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if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) {
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arm_lut[armIdx(opcode)](self, &self.bus, opcode);
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}
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}
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}
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pub fn handleInterrupt(self: *Self) void {
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const should_handle = self.bus.io.ie.raw & self.bus.io.irq.raw;
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if (should_handle != 0) {
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self.bus.io.haltcnt = .Execute;
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// log.debug("An Interrupt was Fired!", .{});
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// Either IME is not true or I in CPSR is true
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// Don't handle interrupts
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if (!self.bus.io.ime or self.cpsr.i.read()) return;
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// log.debug("An interrupt was Handled!", .{});
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// retAddr.gba says r15 on it's own is off by -04h in both ARM and THUMB mode
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const r15 = self.r[15] + 4;
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const cpsr = self.cpsr.raw;
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self.changeMode(.Irq);
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self.cpsr.t.write(false);
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self.cpsr.i.write(true);
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self.r[14] = r15;
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self.spsr.raw = cpsr;
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self.r[15] = 0x000_0018;
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}
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}
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inline fn fetch(self: *Self, comptime T: type) T {
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comptime std.debug.assert(T == u32 or T == u16); // Opcode may be 32-bit (ARM) or 16-bit (THUMB)
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defer self.r[15] += if (T == u32) 4 else 2;
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return self.bus.read(T, self.r[15]);
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}
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pub fn fakePC(self: *const Self) u32 {
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return self.r[15] + 4;
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}
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fn debug_log(self: *const Self, file: *const File, opcode: u32) void {
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if (self.binary_log) {
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self.skyLog(file) catch unreachable;
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} else {
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self.mgbaLog(file, opcode) catch unreachable;
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}
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}
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pub fn panic(self: *const Self, comptime format: []const u8, args: anytype) noreturn {
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var i: usize = 0;
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while (i < 16) : (i += 4) {
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const i_1 = i + 1;
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const i_2 = i + 2;
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const i_3 = i + 3;
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std.debug.print("R{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\n", .{ i, self.r[i], i_1, self.r[i_1], i_2, self.r[i_2], i_3, self.r[i_3] });
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}
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std.debug.print("cpsr: 0x{X:0>8} ", .{self.cpsr.raw});
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prettyPrintPsr(&self.cpsr);
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std.debug.print("spsr: 0x{X:0>8} ", .{self.spsr.raw});
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prettyPrintPsr(&self.spsr);
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if (self.cpsr.t.read()) {
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const opcode = self.bus.read(u16, self.r[15] - 4);
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const id = thumbIdx(opcode);
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std.debug.print("opcode: ID: 0x{b:0>10} 0x{X:0>4}\n", .{ id, opcode });
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} else {
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const opcode = self.bus.read(u32, self.r[15] - 4);
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const id = armIdx(opcode);
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std.debug.print("opcode: ID: 0x{X:0>3} 0x{X:0>8}\n", .{ id, opcode });
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}
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std.debug.print("tick: {}\n\n", .{self.sched.tick});
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std.debug.panic(format, args);
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}
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fn prettyPrintPsr(psr: *const PSR) void {
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std.debug.print("[", .{});
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if (psr.n.read()) std.debug.print("N", .{}) else std.debug.print("-", .{});
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if (psr.z.read()) std.debug.print("Z", .{}) else std.debug.print("-", .{});
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if (psr.c.read()) std.debug.print("C", .{}) else std.debug.print("-", .{});
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if (psr.v.read()) std.debug.print("V", .{}) else std.debug.print("-", .{});
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if (psr.i.read()) std.debug.print("I", .{}) else std.debug.print("-", .{});
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if (psr.f.read()) std.debug.print("F", .{}) else std.debug.print("-", .{});
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if (psr.t.read()) std.debug.print("T", .{}) else std.debug.print("-", .{});
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std.debug.print("|", .{});
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if (getMode(psr.mode.read())) |mode| std.debug.print("{s}", .{modeString(mode)}) else std.debug.print("---", .{});
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std.debug.print("]\n", .{});
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}
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fn modeString(mode: Mode) []const u8 {
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return switch (mode) {
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.User => "usr",
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.Fiq => "fiq",
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.Irq => "irq",
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.Supervisor => "svc",
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.Abort => "abt",
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.Undefined => "und",
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.System => "sys",
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};
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}
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fn skyLog(self: *const Self, file: *const File) !void {
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var buf: [18 * @sizeOf(u32)]u8 = undefined;
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// Write Registers
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var i: usize = 0;
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while (i < 0x10) : (i += 1) {
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skyWrite(&buf, i, self.r[i]);
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}
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skyWrite(&buf, 0x10, self.cpsr.raw);
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skyWrite(&buf, 0x11, if (self.hasSPSR()) self.spsr.raw else self.cpsr.raw);
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_ = try file.writeAll(&buf);
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}
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fn skyWrite(buf: []u8, i: usize, num: u32) void {
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buf[(@sizeOf(u32) * i) + 3] = @truncate(u8, num >> 24 & 0xFF);
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buf[(@sizeOf(u32) * i) + 2] = @truncate(u8, num >> 16 & 0xFF);
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buf[(@sizeOf(u32) * i) + 1] = @truncate(u8, num >> 8 & 0xFF);
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buf[(@sizeOf(u32) * i) + 0] = @truncate(u8, num >> 0 & 0xFF);
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}
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fn mgbaLog(self: *const Self, file: *const File, opcode: u32) !void {
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const thumb_fmt = "{X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} cpsr: {X:0>8} | {X:0>4}:\n";
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const arm_fmt = "{X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} cpsr: {X:0>8} | {X:0>8}:\n";
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var buf: [0x100]u8 = [_]u8{0x00} ** 0x100; // this is larger than it needs to be
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const r0 = self.r[0];
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const r1 = self.r[1];
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const r2 = self.r[2];
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const r3 = self.r[3];
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const r4 = self.r[4];
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const r5 = self.r[5];
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const r6 = self.r[6];
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const r7 = self.r[7];
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const r8 = self.r[8];
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const r9 = self.r[9];
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const r10 = self.r[10];
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const r11 = self.r[11];
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const r12 = self.r[12];
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const r13 = self.r[13];
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const r14 = self.r[14];
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const r15 = self.r[15];
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const c_psr = self.cpsr.raw;
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var log_str: []u8 = undefined;
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if (self.cpsr.t.read()) {
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if (opcode >> 11 == 0x1E) {
|
|
// Instruction 1 of a BL Opcode, print in ARM mode
|
|
const other_half = self.bus.debugRead(u16, self.r[15]);
|
|
const bl_opcode = @as(u32, opcode) << 16 | other_half;
|
|
|
|
log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, bl_opcode });
|
|
} else {
|
|
log_str = try std.fmt.bufPrint(&buf, thumb_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode });
|
|
}
|
|
} else {
|
|
log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode });
|
|
}
|
|
|
|
_ = try file.writeAll(log_str);
|
|
}
|
|
};
|
|
|
|
inline fn armIdx(opcode: u32) u12 {
|
|
return @truncate(u12, opcode >> 20 & 0xFF) << 4 | @truncate(u12, opcode >> 4 & 0xF);
|
|
}
|
|
|
|
inline fn thumbIdx(opcode: u16) u10 {
|
|
return @truncate(u10, opcode >> 6);
|
|
}
|
|
|
|
pub fn checkCond(cpsr: PSR, cond: u4) bool {
|
|
// TODO: Should I implement an enum?
|
|
return switch (cond) {
|
|
0x0 => cpsr.z.read(), // EQ - Equal
|
|
0x1 => !cpsr.z.read(), // NE - Not equal
|
|
0x2 => cpsr.c.read(), // CS - Unsigned higher or same
|
|
0x3 => !cpsr.c.read(), // CC - Unsigned lower
|
|
0x4 => cpsr.n.read(), // MI - Negative
|
|
0x5 => !cpsr.n.read(), // PL - Positive or zero
|
|
0x6 => cpsr.v.read(), // VS - Overflow
|
|
0x7 => !cpsr.v.read(), // VC - No overflow
|
|
0x8 => cpsr.c.read() and !cpsr.z.read(), // HI - unsigned higher
|
|
0x9 => !cpsr.c.read() or cpsr.z.read(), // LS - unsigned lower or same
|
|
0xA => cpsr.n.read() == cpsr.v.read(), // GE - Greater or equal
|
|
0xB => cpsr.n.read() != cpsr.v.read(), // LT - Less than
|
|
0xC => !cpsr.z.read() and (cpsr.n.read() == cpsr.v.read()), // GT - Greater than
|
|
0xD => cpsr.z.read() or (cpsr.n.read() != cpsr.v.read()), // LE - Less than or equal
|
|
0xE => true, // AL - Always
|
|
0xF => false, // NV - Never (reserved in ARMv3 and up, but seems to have not changed?)
|
|
};
|
|
}
|
|
|
|
fn thumbPopulate() [0x400]ThumbInstrFn {
|
|
return comptime {
|
|
@setEvalBranchQuota(5025); // This is exact
|
|
var lut = [_]ThumbInstrFn{thumbUndefined} ** 0x400;
|
|
|
|
var i: usize = 0;
|
|
while (i < lut.len) : (i += 1) {
|
|
lut[i] = switch (@as(u3, i >> 7 & 0x7)) {
|
|
0b000 => if (i >> 5 & 0x3 == 0b11) blk: {
|
|
const I = i >> 4 & 1 == 1;
|
|
const is_sub = i >> 3 & 1 == 1;
|
|
const rn = i & 0x7;
|
|
break :blk format2(I, is_sub, rn);
|
|
} else blk: {
|
|
const op = i >> 5 & 0x3;
|
|
const offset = i & 0x1F;
|
|
break :blk format1(op, offset);
|
|
},
|
|
0b001 => blk: {
|
|
const op = i >> 5 & 0x3;
|
|
const rd = i >> 2 & 0x7;
|
|
break :blk format3(op, rd);
|
|
},
|
|
0b010 => switch (@as(u2, i >> 5 & 0x3)) {
|
|
0b00 => if (i >> 4 & 1 == 1) blk: {
|
|
const op = i >> 2 & 0x3;
|
|
const h1 = i >> 1 & 1;
|
|
const h2 = i & 1;
|
|
break :blk format5(op, h1, h2);
|
|
} else blk: {
|
|
const op = i & 0xF;
|
|
break :blk format4(op);
|
|
},
|
|
0b01 => blk: {
|
|
const rd = i >> 2 & 0x7;
|
|
break :blk format6(rd);
|
|
},
|
|
else => blk: {
|
|
const op = i >> 4 & 0x3;
|
|
const T = i >> 3 & 1 == 1;
|
|
break :blk format78(op, T);
|
|
},
|
|
},
|
|
0b011 => blk: {
|
|
const B = i >> 6 & 1 == 1;
|
|
const L = i >> 5 & 1 == 1;
|
|
const offset = i & 0x1F;
|
|
break :blk format9(B, L, offset);
|
|
},
|
|
else => switch (@as(u3, i >> 6 & 0x7)) {
|
|
// MSB is guaranteed to be 1
|
|
0b000 => blk: {
|
|
const L = i >> 5 & 1 == 1;
|
|
const offset = i & 0x1F;
|
|
break :blk format10(L, offset);
|
|
},
|
|
0b001 => blk: {
|
|
const L = i >> 5 & 1 == 1;
|
|
const rd = i >> 2 & 0x7;
|
|
break :blk format11(L, rd);
|
|
},
|
|
0b010 => blk: {
|
|
const isSP = i >> 5 & 1 == 1;
|
|
const rd = i >> 2 & 0x7;
|
|
break :blk format12(isSP, rd);
|
|
},
|
|
0b011 => if (i >> 4 & 1 == 1) blk: {
|
|
const L = i >> 5 & 1 == 1;
|
|
const R = i >> 2 & 1 == 1;
|
|
break :blk format14(L, R);
|
|
} else blk: {
|
|
const S = i >> 1 & 1 == 1;
|
|
break :blk format13(S);
|
|
},
|
|
0b100 => blk: {
|
|
const L = i >> 5 & 1 == 1;
|
|
const rb = i >> 2 & 0x7;
|
|
|
|
break :blk format15(L, rb);
|
|
},
|
|
0b101 => if (i >> 2 & 0xF == 0b1111) blk: {
|
|
break :blk thumbSoftwareInterrupt();
|
|
} else blk: {
|
|
const cond = i >> 2 & 0xF;
|
|
break :blk format16(cond);
|
|
},
|
|
0b110 => format18(),
|
|
0b111 => blk: {
|
|
const is_low = i >> 5 & 1 == 1;
|
|
break :blk format19(is_low);
|
|
},
|
|
},
|
|
};
|
|
}
|
|
|
|
return lut;
|
|
};
|
|
}
|
|
|
|
fn armPopulate() [0x1000]ArmInstrFn {
|
|
return comptime {
|
|
@setEvalBranchQuota(0xE000);
|
|
var lut = [_]ArmInstrFn{armUndefined} ** 0x1000;
|
|
|
|
var i: usize = 0;
|
|
while (i < lut.len) : (i += 1) {
|
|
lut[i] = switch (@as(u2, i >> 10)) {
|
|
0b00 => if (i == 0x121) blk: {
|
|
break :blk branchAndExchange;
|
|
} else if (i & 0xFCF == 0x009) blk: {
|
|
const A = i >> 5 & 1 == 1;
|
|
const S = i >> 4 & 1 == 1;
|
|
break :blk multiply(A, S);
|
|
} else if (i & 0xFBF == 0x109) blk: {
|
|
const B = i >> 6 & 1 == 1;
|
|
break :blk singleDataSwap(B);
|
|
} else if (i & 0xF8F == 0x089) blk: {
|
|
const U = i >> 6 & 1 == 1;
|
|
const A = i >> 5 & 1 == 1;
|
|
const S = i >> 4 & 1 == 1;
|
|
break :blk multiplyLong(U, A, S);
|
|
} else if (i & 0xE49 == 0x009 or i & 0xE49 == 0x049) blk: {
|
|
const P = i >> 8 & 1 == 1;
|
|
const U = i >> 7 & 1 == 1;
|
|
const I = i >> 6 & 1 == 1;
|
|
const W = i >> 5 & 1 == 1;
|
|
const L = i >> 4 & 1 == 1;
|
|
break :blk halfAndSignedDataTransfer(P, U, I, W, L);
|
|
} else if (i & 0xD90 == 0x100) blk: {
|
|
const I = i >> 9 & 1 == 1;
|
|
const R = i >> 6 & 1 == 1;
|
|
const kind = i >> 4 & 0x3;
|
|
break :blk psrTransfer(I, R, kind);
|
|
} else blk: {
|
|
const I = i >> 9 & 1 == 1;
|
|
const S = i >> 4 & 1 == 1;
|
|
const instrKind = i >> 5 & 0xF;
|
|
break :blk dataProcessing(I, S, instrKind);
|
|
},
|
|
0b01 => if (i >> 9 & 1 == 1 and i & 1 == 1) armUndefined else blk: {
|
|
const I = i >> 9 & 1 == 1;
|
|
const P = i >> 8 & 1 == 1;
|
|
const U = i >> 7 & 1 == 1;
|
|
const B = i >> 6 & 1 == 1;
|
|
const W = i >> 5 & 1 == 1;
|
|
const L = i >> 4 & 1 == 1;
|
|
break :blk singleDataTransfer(I, P, U, B, W, L);
|
|
},
|
|
else => switch (@as(u2, i >> 9 & 0x3)) {
|
|
// MSB is guaranteed to be 1
|
|
0b00 => blk: {
|
|
const P = i >> 8 & 1 == 1;
|
|
const U = i >> 7 & 1 == 1;
|
|
const S = i >> 6 & 1 == 1;
|
|
const W = i >> 5 & 1 == 1;
|
|
const L = i >> 4 & 1 == 1;
|
|
break :blk blockDataTransfer(P, U, S, W, L);
|
|
},
|
|
0b01 => blk: {
|
|
const L = i >> 8 & 1 == 1;
|
|
break :blk branch(L);
|
|
},
|
|
0b10 => armUndefined, // COP Data Transfer
|
|
0b11 => if (i >> 8 & 1 == 1) armSoftwareInterrupt() else armUndefined, // COP Data Operation + Register Transfer
|
|
},
|
|
};
|
|
}
|
|
|
|
return lut;
|
|
};
|
|
}
|
|
|
|
pub const PSR = extern union {
|
|
mode: Bitfield(u32, 0, 5),
|
|
t: Bit(u32, 5),
|
|
f: Bit(u32, 6),
|
|
i: Bit(u32, 7),
|
|
v: Bit(u32, 28),
|
|
c: Bit(u32, 29),
|
|
z: Bit(u32, 30),
|
|
n: Bit(u32, 31),
|
|
raw: u32,
|
|
};
|
|
|
|
const Mode = enum(u5) {
|
|
User = 0b10000,
|
|
Fiq = 0b10001,
|
|
Irq = 0b10010,
|
|
Supervisor = 0b10011,
|
|
Abort = 0b10111,
|
|
Undefined = 0b11011,
|
|
System = 0b11111,
|
|
};
|
|
|
|
const BankedKind = enum(u1) {
|
|
R13 = 0,
|
|
R14,
|
|
};
|
|
|
|
fn getMode(bits: u5) ?Mode {
|
|
return std.meta.intToEnum(Mode, bits) catch null;
|
|
}
|
|
|
|
fn getModeChecked(cpu: *const Arm7tdmi, bits: u5) Mode {
|
|
return getMode(bits) orelse cpu.panic("[CPU/CPSR] 0b{b:0>5} is an invalid CPU mode", .{bits});
|
|
}
|
|
|
|
fn armUndefined(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
|
|
const id = armIdx(opcode);
|
|
cpu.panic("[CPU/Decode] ID: 0x{X:0>3} 0x{X:0>8} is an illegal opcode", .{ id, opcode });
|
|
}
|
|
|
|
fn thumbUndefined(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
|
const id = thumbIdx(opcode);
|
|
cpu.panic("[CPU/Decode] ID: 0b{b:0>10} 0x{X:0>2} is an illegal opcode", .{ id, opcode });
|
|
}
|