109 lines
4.3 KiB
Zig
109 lines
4.3 KiB
Zig
const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
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const adc = @import("../arm/data_processing.zig").adc;
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const sbc = @import("../arm/data_processing.zig").sbc;
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const lsl = @import("../barrel_shifter.zig").lsl;
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const lsr = @import("../barrel_shifter.zig").lsr;
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const asr = @import("../barrel_shifter.zig").asr;
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const ror = @import("../barrel_shifter.zig").ror;
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pub fn fmt4(comptime op: u4) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const rs = opcode >> 3 & 0x7;
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const rd = opcode & 0x7;
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const carry = @boolToInt(cpu.cpsr.c.read());
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const op1 = cpu.r[rd];
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const op2 = cpu.r[rs];
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var result: u32 = undefined;
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var overflow: u1 = undefined;
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switch (op) {
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0x0 => result = op1 & op2, // AND
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0x1 => result = op1 ^ op2, // EOR
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0x2 => result = lsl(true, &cpu.cpsr, op1, @truncate(u8, op2)), // LSL
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0x3 => result = lsr(true, &cpu.cpsr, op1, @truncate(u8, op2)), // LSR
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0x4 => result = asr(true, &cpu.cpsr, op1, @truncate(u8, op2)), // ASR
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0x5 => result = adc(&overflow, op1, op2, carry), // ADC
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0x6 => result = sbc(op1, op2, carry), // SBC
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0x7 => result = ror(true, &cpu.cpsr, op1, @truncate(u8, op2)), // ROR
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0x8 => result = op1 & op2, // TST
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0x9 => result = 0 -% op2, // NEG
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0xA => result = op1 -% op2, // CMP
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0xB => {
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// CMN
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const tmp = @addWithOverflow(op1, op2);
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result = tmp[0];
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overflow = tmp[1];
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},
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0xC => result = op1 | op2, // ORR
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0xD => result = @truncate(u32, @as(u64, op2) * @as(u64, op1)),
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0xE => result = op1 & ~op2,
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0xF => result = ~op2,
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}
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// Write to Destination Register
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switch (op) {
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0x8, 0xA, 0xB => {},
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else => cpu.r[rd] = result,
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}
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// Write Flags
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switch (op) {
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0x0, 0x1, 0x2, 0x3, 0x4, 0x7, 0xC, 0xE, 0xF => {
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// Logic Operations
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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},
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0x8, 0xA => {
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// Test Flags
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// CMN (0xB) is handled with ADC
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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if (op == 0xA) {
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// CMP specific
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cpu.cpsr.c.write(op2 <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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}
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},
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0x5, 0xB => {
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// ADC, CMN
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(overflow == 0b1);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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},
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0x6 => {
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// SBC
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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const subtrahend = @as(u64, op2) -% carry +% 1;
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cpu.cpsr.c.write(subtrahend <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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},
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0x9 => {
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// NEG
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(op2 <= 0);
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cpu.cpsr.v.write(((0 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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},
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0xD => {
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// Multiplication
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// V is unaffected, assuming similar behaviour to ARMv4 MUL C is undefined
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},
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}
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}
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}.inner;
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}
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