52 lines
1.9 KiB
Zig
52 lines
1.9 KiB
Zig
const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
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const shifter = @import("../barrel_shifter.zig");
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const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
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pub fn format1(comptime op: u2, comptime offset: u5) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const rs = opcode >> 3 & 0x7;
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const rd = opcode & 0x7;
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const result = switch (op) {
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0b00 => blk: {
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// LSL
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if (offset == 0) {
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break :blk cpu.r[rs];
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} else {
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break :blk shifter.logicalLeft(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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0b01 => blk: {
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// LSR
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if (offset == 0) {
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cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
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break :blk @as(u32, 0);
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} else {
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break :blk shifter.logicalRight(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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0b10 => blk: {
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// ASR
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if (offset == 0) {
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cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
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break :blk @bitCast(u32, @bitCast(i32, cpu.r[rs]) >> 31);
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} else {
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break :blk shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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else => cpu.panic("[CPU|THUMB|Fmt1] {} is an invalid op", .{op}),
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};
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// Equivalent to an ARM MOVS
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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}
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}.inner;
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}
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