60 lines
2.3 KiB
Zig
60 lines
2.3 KiB
Zig
const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").arm.InstrFn;
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const PSR = @import("../../cpu.zig").PSR;
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const log = std.log.scoped(.PsrTransfer);
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const rotr = @import("zba-util").rotr;
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pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
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switch (kind) {
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0b00 => {
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// MRS
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const rd = opcode >> 12 & 0xF;
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if (R and !cpu.hasSPSR()) log.err("Tried to read SPSR from User/System Mode", .{});
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cpu.r[rd] = if (R) cpu.spsr.raw else cpu.cpsr.raw;
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},
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0b10 => {
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// MSR
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const field_mask = @truncate(u4, opcode >> 16 & 0xF);
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const rm_idx = opcode & 0xF;
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const right = if (I) rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) * 2) else cpu.r[rm_idx];
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if (R and !cpu.hasSPSR()) log.err("Tried to write to SPSR in User/System Mode", .{});
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if (R) {
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// arm.gba seems to expect the SPSR to do somethign in SYS mode,
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// so we just assume that despite writing to the SPSR in USR or SYS mode
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// being UNPREDICTABLE, it just magically has a working SPSR somehow
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cpu.spsr.raw = fieldMask(&cpu.spsr, field_mask, right);
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} else {
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if (cpu.isPrivileged()) cpu.setCpsr(fieldMask(&cpu.cpsr, field_mask, right));
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}
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},
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else => cpu.panic("[CPU/PSR Transfer] Bits 21:220 of {X:0>8} are undefined", .{opcode}),
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}
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}
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}.inner;
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}
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fn fieldMask(psr: *const PSR, field_mask: u4, right: u32) u32 {
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// This bitwise ORs bits 3 and 0 of the field mask into a u2
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// We do this because we only care about bits 7:0 and 31:28 of the CPSR
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const bits = @truncate(u2, (field_mask >> 2 & 0x2) | (field_mask & 1));
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const mask: u32 = switch (bits) {
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0b00 => 0x0000_0000,
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0b01 => 0x0000_00FF,
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0b10 => 0xF000_0000,
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0b11 => 0xF000_00FF,
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};
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return (psr.raw & ~mask) | (right & mask);
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}
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