src/cpu/block_data_transfer.zig

@@ -8,42 +8,27 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
     return struct {
         fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
             const rn = opcode >> 16 & 0xF;
-            const base = cpu.r[rn];
+            var base = cpu.r[rn];
 
+            // TODO: For Performance (?) if U we got from 0 -> 0xF, if !U, 0xF -> 0
+            // we can do this and have it be fast because of comptime, baby!
+
+            if (!U) {
+                var count: u32 = 0;
+                var i: u5 = 0;
+                while (i < 0x10) : (i += 1) {
+                    count += opcode >> i & 1;
+                }
+
+                base -= count * 4;
+            }
+
+            var address = if (@boolToInt(P) ^ @boolToInt(U) == 0) base + 4 else base;
             if (S and opcode >> 15 & 1 == 0) std.debug.panic("[CPU] TODO: STM/LDM with S set but R15 not in transfer list", .{});
 
-            if (U) {
-                // Increment
-                var address = if (P) base + 4 else base;
-
             var i: u5 = 0;
             while (i < 0x10) : (i += 1) {
                 if (opcode >> i & 1 == 1) {
-                        transfer(cpu, bus, i, address);
-                        address += 4;
-                    }
-                }
-
-                if (W and P or !P) cpu.r[rn] = address - 4;
-            } else {
-                // Decrement
-                var address = if (P) base - 4 else base;
-
-                var i: u5 = 0x10;
-                while (i > 0) : (i -= 1) {
-                    const reg_idx = i - 1;
-
-                    if (opcode >> reg_idx & 1 == 1) {
-                        transfer(cpu, bus, reg_idx, address);
-                        address -= 4;
-                    }
-                }
-
-                if (W and P or !P) cpu.r[rn] = address + 4;
-            }
-        }
-
-        fn transfer(cpu: *Arm7tdmi, bus: *Bus, i: u5, address: u32) void {
                     if (L) {
                         cpu.r[i] = bus.read32(address);
                         if (S and i == 0xF) std.debug.panic("[CPU] TODO: SPSR_<mode> is transferred to CPSR", .{});
@@ -59,6 +44,12 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
                             bus.write32(address, cpu.r[i]);
                         }
                     }
+
+                    address += 4;
+                }
+            }
+
+            if (W and P or !P) cpu.r[rn] = if (U) address - 4 else base;
         }
     }.inner;
 }

src/ppu.zig

@@ -53,16 +53,18 @@ pub const Ppu = struct {
                 const frame_select = io.dispcnt.frame_select.read();
 
                 const fb_start = buf_pitch * @as(usize, scanline);
-                const vram_start = fb_start >> 1;
+                const vram_start = width * @as(usize, scanline);
 
                 const start = if (frame_select) 0xA000 + vram_start else vram_start;
                 const end = start + width;
 
                 for (self.vram.buf[start..end]) |byte, i| {
                     const fb_i = i * @sizeOf(u16);
+                    const colour = self.palette.buf[byte];
+                    var bgr555: u16 = colour & 0x3 | (colour & 0x1C >> 2) << 5 | @as(u16, colour >> 5) << 10;
 
-                    self.frame_buf[fb_start + fb_i + 1] = self.palette.buf[byte + 1];
+                    self.frame_buf[fb_start + fb_i + 1] = @truncate(u8, bgr555 >> 8);
-                    self.frame_buf[fb_start + fb_i] = self.palette.buf[byte];
+                    self.frame_buf[fb_start + fb_i] = @truncate(u8, bgr555);
                 }
             },
             else => std.debug.panic("[PPU] TODO: Implement BG Mode {}", .{bg_mode}),