chore: dont allocate not-small ?Sprite array on stack

use memset like most other allocations in this emu

src/core/Bus.zig

@@ -169,7 +169,7 @@ fn openBus(self: *const Self, comptime T: type, address: u32) T {
         }
     };
 
-    return @truncate(T, word);
+    return @truncate(T, rotr(u32, word, 8 * (address & 3)));
 }
 
 pub fn read(self: *Self, comptime T: type, address: u32) T {

src/core/bus/Bios.zig

@@ -19,7 +19,7 @@ pub fn read(self: *Self, comptime T: type, r15: u32, addr: u32) T {
     }
 
     log.debug("Rejected read since r15=0x{X:0>8}", .{r15});
-    return @truncate(T, self._read(T, self.addr_latch));
+    return @truncate(T, self._read(T, self.addr_latch + 8));
 }
 
 pub fn dbgRead(self: *const Self, comptime T: type, r15: u32, addr: u32) T {

src/core/bus/dma.zig

@@ -11,8 +11,6 @@ const log = std.log.scoped(.DmaTransfer);
 const setHi = util.setHi;
 const setLo = util.setLo;
 
-const rotr = @import("../../util.zig").rotr;
-
 pub fn create() DmaTuple {
     return .{ DmaController(0).init(), DmaController(1).init(), DmaController(2).init(), DmaController(3).init() };
 }
@@ -101,7 +99,6 @@ fn DmaController(comptime id: u2) type {
 
         const sad_mask: u32 = if (id == 0) 0x07FF_FFFF else 0x0FFF_FFFF;
         const dad_mask: u32 = if (id != 3) 0x07FF_FFFF else 0x0FFF_FFFF;
-        const WordCount = if (id == 3) u16 else u14;
 
         /// Write-only. The first address in a DMA transfer. (DMASAD)
         /// Note: use writeSrc instead of manipulating src_addr directly
@@ -110,19 +107,17 @@ fn DmaController(comptime id: u2) type {
         /// Note: Use writeDst instead of manipulatig dst_addr directly
         dad: u32,
         /// Write-only. The Word Count for the DMA Transfer (DMACNT_L)
-        word_count: WordCount,
+        word_count: if (id == 3) u16 else u14,
         /// Read / Write. DMACNT_H
         /// Note: Use writeControl instead of manipulating cnt directly.
         cnt: DmaControl,
 
-        /// Internal. The last successfully read value
-        data_latch: u32,
         /// Internal. Currrent Source Address
         sad_latch: u32,
         /// Internal. Current Destination Address
         dad_latch: u32,
         /// Internal. Word Count
-        _word_count: WordCount,
+        _word_count: if (id == 3) u16 else u14,
 
         /// Some DMA Transfers are enabled during Hblank / VBlank and / or
         /// have delays. Thefore bit 15 of DMACNT isn't actually something
@@ -139,8 +134,6 @@ fn DmaController(comptime id: u2) type {
                 // Internals
                 .sad_latch = 0,
                 .dad_latch = 0,
-                .data_latch = 0,
-
                 ._word_count = 0,
                 .in_progress = false,
             };
@@ -165,7 +158,7 @@ fn DmaController(comptime id: u2) type {
                 // Reload Internals on Rising Edge.
                 self.sad_latch = self.sad;
                 self.dad_latch = self.dad;
-                self._word_count = if (self.word_count == 0) std.math.maxInt(WordCount) else self.word_count;
+                self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
 
                 // Only a Start Timing of 00 has a DMA Transfer immediately begin
                 self.in_progress = new.start_timing.read() == 0b00;
@@ -188,19 +181,11 @@ fn DmaController(comptime id: u2) type {
             const offset: u32 = if (transfer_type) @sizeOf(u32) else @sizeOf(u16);
 
             const mask = if (transfer_type) ~@as(u32, 3) else ~@as(u32, 1);
-            const sad_addr = self.sad_latch & mask;
-            const dad_addr = self.dad_latch & mask;
 
             if (transfer_type) {
-                if (sad_addr >= 0x0200_0000) self.data_latch = cpu.bus.read(u32, sad_addr);
+                cpu.bus.write(u32, self.dad_latch & mask, cpu.bus.read(u32, self.sad_latch & mask));
-                cpu.bus.write(u32, dad_addr, self.data_latch);
             } else {
-                if (sad_addr >= 0x0200_0000) {
+                cpu.bus.write(u16, self.dad_latch & mask, cpu.bus.read(u16, self.sad_latch & mask));
-                    const value: u32 = cpu.bus.read(u16, sad_addr);
-                    self.data_latch = value << 16 | value;
-                }
-
-                cpu.bus.write(u16, dad_addr, @truncate(u16, rotr(u32, self.data_latch, 8 * (dad_addr & 3))));
             }
 
             switch (sad_adj) {

src/core/bus/io.zig

@@ -11,8 +11,8 @@ const Bus = @import("../Bus.zig");
 const DmaController = @import("dma.zig").DmaController;
 const Scheduler = @import("../scheduler.zig").Scheduler;
 
-const setHi = util.setHi;
+const setHi = util.setLo;
-const setLo = util.setLo;
+const setLo = util.setHi;
 
 const log = std.log.scoped(.@"I/O");
 

src/core/cpu/arm/half_signed_data_transfer.zig

@@ -35,8 +35,11 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
                     },
                     0b11 => {
                         // LDRSH
-                        const value = bus.read(u16, address);
+                        result = if (address & 1 == 1) blk: {
-                        result = if (address & 1 == 1) sext(u32, u8, @truncate(u8, value >> 8)) else sext(u32, u16, value);
+                            break :blk sext(u32, u8, bus.read(u8, address));
+                        } else blk: {
+                            break :blk sext(u32, u16, bus.read(u16, address));
+                        };
                     },
                     0b00 => unreachable, // SWP
                 }

src/core/cpu/thumb/data_transfer.zig

@@ -46,8 +46,11 @@ pub fn fmt78(comptime op: u2, comptime T: bool) InstrFn {
                     },
                     0b11 => {
                         // LDRSH
-                        const value = bus.read(u16, address);
+                        cpu.r[rd] = if (address & 1 == 1) blk: {
-                        cpu.r[rd] = if (address & 1 == 1) sext(u32, u8, @truncate(u8, value >> 8)) else sext(u32, u16, value);
+                            break :blk sext(u32, u8, bus.read(u8, address));
+                        } else blk: {
+                            break :blk sext(u32, u16, bus.read(u16, address));
+                        };
                     },
                 }
             } else {

src/util.zig

@@ -276,7 +276,7 @@ pub const audio = struct {
 };
 
 /// Sets the high bits of an integer to a value
-pub inline fn setLo(comptime T: type, left: T, right: HalfInt(T)) T {
+pub inline fn setHi(comptime T: type, left: T, right: HalfInt(T)) T {
     return switch (T) {
         u32 => (left & 0xFFFF_0000) | right,
         u16 => (left & 0xFF00) | right,
@@ -286,7 +286,7 @@ pub inline fn setLo(comptime T: type, left: T, right: HalfInt(T)) T {
 }
 
 /// sets the low bits of an integer to a value
-pub inline fn setHi(comptime T: type, left: T, right: HalfInt(T)) T {
+pub inline fn setLo(comptime T: type, left: T, right: HalfInt(T)) T {
     return switch (T) {
         u32 => (left & 0x0000_FFFF) | @as(u32, right) << 16,
         u16 => (left & 0x00FF) | @as(u16, right) << 8,