fix: advance r15, even when the pipeline is reloaded from the scheduler

The PC would fall behind whenever an IRQ was called because the pipeline
was reloaded (+8 to PC), however that was never actually done by any code

Now, the PC is always incremented when the pipeline is reloaded

src/Gui.zig

@@ -53,11 +53,11 @@ pub fn init(title: [12]u8, width: i32, height: i32) Self {
     };
 }
 
-pub fn run(self: *Self, arm7tdmi: *Arm7tdmi, scheduler: *Scheduler) !void {
+pub fn run(self: *Self, cpu: *Arm7tdmi, scheduler: *Scheduler) !void {
     var quit = std.atomic.Atomic(bool).init(false);
     var frame_rate = FpsTracker.init();
 
-    const thread = try std.Thread.spawn(.{}, emu.run, .{ &quit, &frame_rate, scheduler, arm7tdmi });
+    const thread = try std.Thread.spawn(.{}, emu.run, .{ &quit, &frame_rate, scheduler, cpu });
     defer thread.join();
 
     var title_buf: [0x100]u8 = [_]u8{0} ** 0x100;
@@ -68,7 +68,7 @@ pub fn run(self: *Self, arm7tdmi: *Arm7tdmi, scheduler: *Scheduler) !void {
             switch (event.type) {
                 SDL.SDL_QUIT => break :emu_loop,
                 SDL.SDL_KEYDOWN => {
-                    const io = &arm7tdmi.bus.io;
+                    const io = &cpu.bus.io;
                     const key_code = event.key.keysym.sym;
 
                     switch (key_code) {
@@ -86,7 +86,7 @@ pub fn run(self: *Self, arm7tdmi: *Arm7tdmi, scheduler: *Scheduler) !void {
                     }
                 },
                 SDL.SDL_KEYUP => {
-                    const io = &arm7tdmi.bus.io;
+                    const io = &cpu.bus.io;
                     const key_code = event.key.keysym.sym;
 
                     switch (key_code) {
@@ -100,12 +100,12 @@ pub fn run(self: *Self, arm7tdmi: *Arm7tdmi, scheduler: *Scheduler) !void {
                         SDL.SDLK_s => io.keyinput.shoulder_r.set(),
                         SDL.SDLK_RETURN => io.keyinput.start.set(),
                         SDL.SDLK_RSHIFT => io.keyinput.select.set(),
-                        SDL.SDLK_i => log.err("Sample Count: {}", .{@intCast(u32, SDL.SDL_AudioStreamAvailable(arm7tdmi.bus.apu.stream)) / (2 * @sizeOf(u16))}),
+                        SDL.SDLK_i => log.err("Sample Count: {}", .{@intCast(u32, SDL.SDL_AudioStreamAvailable(cpu.bus.apu.stream)) / (2 * @sizeOf(u16))}),
                         SDL.SDLK_j => log.err("Scheduler Capacity: {} | Scheduler Event Count: {}", .{ scheduler.queue.capacity(), scheduler.queue.count() }),
                         SDL.SDLK_k => {
                             // Dump IWRAM to file
-                            log.info("PC: 0x{X:0>8}", .{arm7tdmi.r[15]});
-                            log.info("LR: 0x{X:0>8}", .{arm7tdmi.r[14]});
+                            log.info("PC: 0x{X:0>8}", .{cpu.r[15]});
+                            log.info("LR: 0x{X:0>8}", .{cpu.r[14]});
                             // const iwram_file = try std.fs.cwd().createFile("iwram.bin", .{});
                             // defer iwram_file.close();
 
@@ -119,7 +119,7 @@ pub fn run(self: *Self, arm7tdmi: *Arm7tdmi, scheduler: *Scheduler) !void {
         }
 
         // Emulator has an internal Double Buffer
-        const framebuf = arm7tdmi.bus.ppu.framebuf.get(.Renderer);
+        const framebuf = cpu.bus.ppu.framebuf.get(.Renderer);
         _ = SDL.SDL_UpdateTexture(self.texture, null, framebuf.ptr, pitch);
         _ = SDL.SDL_RenderCopy(self.renderer, self.texture, null, null);
         SDL.SDL_RenderPresent(self.renderer);
@@ -136,12 +136,13 @@ pub fn initAudio(self: *Self, apu: *Apu) void {
     self.audio.?.play();
 }
 
-pub fn deinit(self: Self) void {
-    if (self.audio) |aud| aud.deinit();
+pub fn deinit(self: *Self) void {
+    if (self.audio) |*aud| aud.deinit();
     SDL.SDL_DestroyTexture(self.texture);
     SDL.SDL_DestroyRenderer(self.renderer);
     SDL.SDL_DestroyWindow(self.window);
     SDL.SDL_Quit();
+    self.* = undefined;
 }
 
 const Audio = struct {
@@ -168,12 +169,13 @@ const Audio = struct {
         };
     }
 
-    fn deinit(this: This) void {
-        SDL.SDL_CloseAudioDevice(this.device);
+    fn deinit(self: *This) void {
+        SDL.SDL_CloseAudioDevice(self.device);
+        self.* = undefined;
     }
 
-    pub fn play(this: *This) void {
-        SDL.SDL_PauseAudioDevice(this.device, 0);
+    pub fn play(self: *This) void {
+        SDL.SDL_PauseAudioDevice(self.device, 0);
     }
 
     export fn callback(userdata: ?*anyopaque, stream: [*c]u8, len: c_int) void {

src/core/Bus.zig

@@ -49,32 +49,29 @@ io: Io,
 cpu: ?*Arm7tdmi,
 sched: *Scheduler,
 
-pub fn init(alloc: Allocator, sched: *Scheduler, paths: FilePaths) !Self {
-    return Self{
-        .pak = try GamePak.init(alloc, paths.rom, paths.save),
-        .bios = try Bios.init(alloc, paths.bios),
-        .ppu = try Ppu.init(alloc, sched),
+pub fn init(self: *Self, allocator: Allocator, sched: *Scheduler, cpu: *Arm7tdmi, paths: FilePaths) !void {
+    self.* = .{
+        .pak = try GamePak.init(allocator, paths.rom, paths.save),
+        .bios = try Bios.init(allocator, paths.bios),
+        .ppu = try Ppu.init(allocator, sched),
         .apu = Apu.init(sched),
-        .iwram = try Iwram.init(alloc),
-        .ewram = try Ewram.init(alloc),
+        .iwram = try Iwram.init(allocator),
+        .ewram = try Ewram.init(allocator),
         .dma = createDmaTuple(),
         .tim = createTimerTuple(sched),
         .io = Io.init(),
-        .cpu = null,
+        .cpu = cpu,
         .sched = sched,
     };
 }
 
-pub fn deinit(self: Self) void {
+pub fn deinit(self: *Self) void {
     self.iwram.deinit();
     self.ewram.deinit();
     self.pak.deinit();
     self.bios.deinit();
     self.ppu.deinit();
-}
-
-pub fn attach(self: *Self, cpu: *Arm7tdmi) void {
-    self.cpu = cpu;
+    self.* = undefined;
 }
 
 pub fn dbgRead(self: *const Self, comptime T: type, address: u32) T {

src/core/apu.zig

@@ -444,29 +444,29 @@ const ToneSweep = struct {
             };
         }
 
-        pub fn tick(this: *This, ch1: *Self) void {
-            if (this.timer != 0) this.timer -= 1;
+        pub fn tick(self: *This, ch1: *Self) void {
+            if (self.timer != 0) self.timer -= 1;
 
-            if (this.timer == 0) {
+            if (self.timer == 0) {
                 const period = ch1.sweep.period.read();
-                this.timer = if (period == 0) 8 else period;
-                if (!this.calc_performed) this.calc_performed = true;
+                self.timer = if (period == 0) 8 else period;
+                if (!self.calc_performed) self.calc_performed = true;
 
-                if (this.enabled and period != 0) {
-                    const new_freq = this.calcFrequency(ch1);
+                if (self.enabled and period != 0) {
+                    const new_freq = self.calcFrequency(ch1);
 
                     if (new_freq <= 0x7FF and ch1.sweep.shift.read() != 0) {
                         ch1.freq.frequency.write(@truncate(u11, new_freq));
-                        this.shadow = @truncate(u11, new_freq);
+                        self.shadow = @truncate(u11, new_freq);
 
-                        _ = this.calcFrequency(ch1);
+                        _ = self.calcFrequency(ch1);
                     }
                 }
             }
         }
 
-        fn calcFrequency(this: *This, ch1: *Self) u12 {
-            const shadow = @as(u12, this.shadow);
+        fn calcFrequency(self: *This, ch1: *Self) u12 {
+            const shadow = @as(u12, self.shadow);
             const shadow_shifted = shadow >> ch1.sweep.shift.read();
             const decrease = ch1.sweep.direction.read();
 

src/core/bus/Bios.zig

@@ -8,27 +8,28 @@ pub const size = 0x4000;
 const Self = @This();
 
 buf: ?[]u8,
-alloc: Allocator,
+allocator: Allocator,
 
 addr_latch: u32,
 
-pub fn init(alloc: Allocator, maybe_path: ?[]const u8) !Self {
+pub fn init(allocator: Allocator, maybe_path: ?[]const u8) !Self {
     const buf: ?[]u8 = if (maybe_path) |path| blk: {
         const file = try std.fs.cwd().openFile(path, .{});
         defer file.close();
 
-        break :blk try file.readToEndAlloc(alloc, try file.getEndPos());
+        break :blk try file.readToEndAlloc(allocator, try file.getEndPos());
     } else null;
 
     return Self{
         .buf = buf,
-        .alloc = alloc,
+        .allocator = allocator,
         .addr_latch = 0,
     };
 }
 
-pub fn deinit(self: Self) void {
-    if (self.buf) |buf| self.alloc.free(buf);
+pub fn deinit(self: *Self) void {
+    if (self.buf) |buf| self.allocator.free(buf);
+    self.* = undefined;
 }
 
 pub fn read(self: *Self, comptime T: type, r15: u32, addr: u32) T {

src/core/bus/Ewram.zig

@@ -5,20 +5,21 @@ const ewram_size = 0x40000;
 const Self = @This();
 
 buf: []u8,
-alloc: Allocator,
+allocator: Allocator,
 
-pub fn init(alloc: Allocator) !Self {
-    const buf = try alloc.alloc(u8, ewram_size);
+pub fn init(allocator: Allocator) !Self {
+    const buf = try allocator.alloc(u8, ewram_size);
     std.mem.set(u8, buf, 0);
 
     return Self{
         .buf = buf,
-        .alloc = alloc,
+        .allocator = allocator,
     };
 }
 
-pub fn deinit(self: Self) void {
-    self.alloc.free(self.buf);
+pub fn deinit(self: *Self) void {
+    self.allocator.free(self.buf);
+    self.* = undefined;
 }
 
 pub fn read(self: *const Self, comptime T: type, address: usize) T {

src/core/bus/GamePak.zig

@@ -8,22 +8,22 @@ const Self = @This();
 
 title: [12]u8,
 buf: []u8,
-alloc: Allocator,
+allocator: Allocator,
 backup: Backup,
 
-pub fn init(alloc: Allocator, rom_path: []const u8, save_path: ?[]const u8) !Self {
+pub fn init(allocator: Allocator, rom_path: []const u8, save_path: ?[]const u8) !Self {
     const file = try std.fs.cwd().openFile(rom_path, .{});
     defer file.close();
 
-    const file_buf = try file.readToEndAlloc(alloc, try file.getEndPos());
+    const file_buf = try file.readToEndAlloc(allocator, try file.getEndPos());
     const title = parseTitle(file_buf);
     const kind = Backup.guessKind(file_buf) orelse .None;
 
     const pak = Self{
         .buf = file_buf,
-        .alloc = alloc,
+        .allocator = allocator,
         .title = title,
-        .backup = try Backup.init(alloc, kind, title, save_path),
+        .backup = try Backup.init(allocator, kind, title, save_path),
     };
     pak.parseHeader();
 
@@ -58,9 +58,10 @@ inline fn isLarge(self: *const Self) bool {
     return self.buf.len > 0x100_0000;
 }
 
-pub fn deinit(self: Self) void {
-    self.alloc.free(self.buf);
+pub fn deinit(self: *Self) void {
     self.backup.deinit();
+    self.allocator.free(self.buf);
+    self.* = undefined;
 }
 
 pub fn read(self: *Self, comptime T: type, address: u32) T {

src/core/bus/Iwram.zig

@@ -5,20 +5,21 @@ const iwram_size = 0x8000;
 const Self = @This();
 
 buf: []u8,
-alloc: Allocator,
+allocator: Allocator,
 
-pub fn init(alloc: Allocator) !Self {
-    const buf = try alloc.alloc(u8, iwram_size);
+pub fn init(allocator: Allocator) !Self {
+    const buf = try allocator.alloc(u8, iwram_size);
     std.mem.set(u8, buf, 0);
 
     return Self{
         .buf = buf,
-        .alloc = alloc,
+        .allocator = allocator,
     };
 }
 
-pub fn deinit(self: Self) void {
-    self.alloc.free(self.buf);
+pub fn deinit(self: *Self) void {
+    self.allocator.free(self.buf);
+    self.* = undefined;
 }
 
 pub fn read(self: *const Self, comptime T: type, address: usize) T {

src/core/bus/backup.zig

@@ -17,7 +17,7 @@ pub const Backup = struct {
     const Self = @This();
 
     buf: []u8,
-    alloc: Allocator,
+    allocator: Allocator,
     kind: Kind,
 
     title: [12]u8,
@@ -49,7 +49,7 @@ pub const Backup = struct {
 
         var backup = Self{
             .buf = buf,
-            .alloc = allocator,
+            .allocator = allocator,
             .kind = kind,
             .title = title,
             .save_path = path,
@@ -74,9 +74,10 @@ pub const Backup = struct {
         return null;
     }
 
-    pub fn deinit(self: Self) void {
-        if (self.save_path) |path| self.writeSaveToDisk(self.alloc, path) catch |e| log.err("Failed to write save: {}", .{e});
-        self.alloc.free(self.buf);
+    pub fn deinit(self: *Self) void {
+        if (self.save_path) |path| self.writeSaveToDisk(self.allocator, path) catch |e| log.err("Failed to write save: {}", .{e});
+        self.allocator.free(self.buf);
+        self.* = undefined;
     }
 
     fn loadSaveFromDisk(self: *Self, allocator: Allocator, path: []const u8) !void {
@@ -309,7 +310,7 @@ const Eeprom = struct {
     writer: Writer,
     reader: Reader,
 
-    alloc: Allocator,
+    allocator: Allocator,
 
     const Kind = enum {
         Unknown,
@@ -325,14 +326,14 @@ const Eeprom = struct {
         RequestEnd,
     };
 
-    fn init(alloc: Allocator) Self {
+    fn init(allocator: Allocator) Self {
         return .{
             .kind = .Unknown,
             .state = .Ready,
             .writer = Writer.init(),
             .reader = Reader.init(),
             .addr = 0,
-            .alloc = alloc,
+            .allocator = allocator,
         };
     }
 
@@ -360,7 +361,7 @@ const Eeprom = struct {
                     else => unreachable,
                 };
 
-                buf.* = self.alloc.alloc(u8, len) catch |e| {
+                buf.* = self.allocator.alloc(u8, len) catch |e| {
                     log.err("Failed to resize EEPROM buf to {} bytes", .{len});
                     std.debug.panic("EEPROM entered irrecoverable state {}", .{e});
                 };

src/core/cpu.zig

@@ -233,6 +233,7 @@ pub const Arm7tdmi = struct {
     const Self = @This();
 
     r: [16]u32,
+    pipe: Pipline,
     sched: *Scheduler,
     bus: *Bus,
     cpsr: PSR,
@@ -250,9 +251,10 @@ pub const Arm7tdmi = struct {
 
     logger: ?Logger,
 
-    pub fn init(sched: *Scheduler, bus: *Bus) Self {
+    pub fn init(sched: *Scheduler, bus: *Bus, log_file: ?std.fs.File) Self {
         return Self{
             .r = [_]u32{0x00} ** 16,
+            .pipe = Pipline.init(),
             .sched = sched,
             .bus = bus,
             .cpsr = .{ .raw = 0x0000_001F },
@@ -260,14 +262,10 @@ pub const Arm7tdmi = struct {
             .banked_fiq = [_]u32{0x00} ** 10,
             .banked_r = [_]u32{0x00} ** 12,
             .banked_spsr = [_]PSR{.{ .raw = 0x0000_0000 }} ** 5,
-            .logger = null,
+            .logger = if (log_file) |file| Logger.init(file) else null,
         };
     }
 
-    pub fn attach(self: *Self, log_file: std.fs.File) void {
-        self.logger = Logger.init(log_file);
-    }
-
     inline fn bankedIdx(mode: Mode, kind: BankedKind) usize {
         const idx: usize = switch (mode) {
             .User, .System => 0,
@@ -316,8 +314,21 @@ pub const Arm7tdmi = struct {
         return self.bus.io.haltcnt == .Halt;
     }
 
+    pub fn setCpsrNoFlush(self: *Self, value: u32) void {
+        if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
+        self.cpsr.raw = value;
+    }
+
     pub fn setCpsr(self: *Self, value: u32) void {
         if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
+
+        const new: PSR = .{ .raw = value };
+        if (self.cpsr.t.read() != new.t.read()) {
+            // If THUMB to ARM or ARM to THUMB, flush pipeline
+            self.r[15] &= if (new.t.read()) ~@as(u32, 1) else ~@as(u32, 3);
+            if (new.t.read()) self.pipe.reload(u16, self) else self.pipe.reload(u32, self);
+        }
+
         self.cpsr.raw = value;
     }
 
@@ -408,31 +419,35 @@ pub const Arm7tdmi = struct {
     pub fn fastBoot(self: *Self) void {
         self.r = std.mem.zeroes([16]u32);
 
-        self.r[0] = 0x08000000;
-        self.r[1] = 0x000000EA;
+        // self.r[0] = 0x08000000;
+        // self.r[1] = 0x000000EA;
         self.r[13] = 0x0300_7F00;
         self.r[15] = 0x0800_0000;
 
         self.banked_r[bankedIdx(.Irq, .R13)] = 0x0300_7FA0;
         self.banked_r[bankedIdx(.Supervisor, .R13)] = 0x0300_7FE0;
 
-        self.cpsr.raw = 0x6000001F;
+        // self.cpsr.raw = 0x6000001F;
+        self.cpsr.raw = 0x0000_001F;
     }
 
     pub fn step(self: *Self) void {
-        if (self.cpsr.t.read()) {
-            const opcode = self.fetch(u16);
+        if (self.cpsr.t.read()) blk: {
+            const opcode = @truncate(u16, self.pipe.step(self, u16) orelse break :blk);
             if (cpu_logging) self.logger.?.mgbaLog(self, opcode);
 
             thumb.lut[thumbIdx(opcode)](self, self.bus, opcode);
-        } else {
-            const opcode = self.fetch(u32);
+        } else blk: {
+            const opcode = self.pipe.step(self, u32) orelse break :blk;
             if (cpu_logging) self.logger.?.mgbaLog(self, opcode);
 
             if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) {
                 arm.lut[armIdx(opcode)](self, self.bus, opcode);
             }
         }
+
+        if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
+        self.pipe.flushed = false;
     }
 
     pub fn stepDmaTransfer(self: *Self) bool {
@@ -467,27 +482,26 @@ pub const Arm7tdmi = struct {
     pub fn handleInterrupt(self: *Self) void {
         const should_handle = self.bus.io.ie.raw & self.bus.io.irq.raw;
 
-        if (should_handle != 0) {
-            self.bus.io.haltcnt = .Execute;
-            // log.debug("An Interrupt was Fired!", .{});
+        // Return if IME is disabled, CPSR I is set or there is nothing to handle
+        if (!self.bus.io.ime or self.cpsr.i.read() or should_handle == 0) return;
 
-            // Either IME is not true or I in CPSR is true
-            // Don't handle interrupts
-            if (!self.bus.io.ime or self.cpsr.i.read()) return;
-            // log.debug("An interrupt was Handled!", .{});
+        // If pipeline isn't full, return but reschedule the handling of the event
+        if (!self.pipe.isFull()) return;
 
-            // retAddr.gba says r15 on it's own is off by -04h in both ARM and THUMB mode
-            const r15 = self.r[15] + 4;
-            const cpsr = self.cpsr.raw;
+        // log.debug("Handling Interrupt!", .{});
+        self.bus.io.haltcnt = .Execute;
 
-            self.changeMode(.Irq);
-            self.cpsr.t.write(false);
-            self.cpsr.i.write(true);
+        const ret_addr = self.r[15] - if (self.cpsr.t.read()) 2 else @as(u32, 4);
+        const new_spsr = self.cpsr.raw;
 
-            self.r[14] = r15;
-            self.spsr.raw = cpsr;
-            self.r[15] = 0x000_0018;
-        }
+        self.changeMode(.Irq);
+        self.cpsr.t.write(false);
+        self.cpsr.i.write(true);
+
+        self.r[14] = ret_addr;
+        self.spsr.raw = new_spsr;
+        self.r[15] = 0x0000_0018;
+        self.pipe.reload(u32, self);
     }
 
     inline fn fetch(self: *Self, comptime T: type) T {
@@ -501,8 +515,12 @@ pub const Arm7tdmi = struct {
         return self.bus.read(T, self.r[15]);
     }
 
-    pub fn fakePC(self: *const Self) u32 {
-        return self.r[15] + 4;
+    fn debug_log(self: *const Self, file: *const File, opcode: u32) void {
+        if (self.binary_log) {
+            self.skyLog(file) catch unreachable;
+        } else {
+            self.mgbaLog(file, opcode) catch unreachable;
+        }
     }
 
     pub fn panic(self: *const Self, comptime format: []const u8, args: anytype) noreturn {
@@ -519,6 +537,8 @@ pub const Arm7tdmi = struct {
         std.debug.print("spsr: 0x{X:0>8} ", .{self.spsr.raw});
         prettyPrintPsr(&self.spsr);
 
+        std.debug.print("pipeline: {??X:0>8}\n", .{self.pipe.stage});
+
         if (self.cpsr.t.read()) {
             const opcode = self.bus.dbgRead(u16, self.r[15] - 4);
             const id = thumbIdx(opcode);
@@ -582,7 +602,7 @@ pub const Arm7tdmi = struct {
         const r12 = self.r[12];
         const r13 = self.r[13];
         const r14 = self.r[14];
-        const r15 = self.r[15];
+        const r15 = self.r[15] -| if (self.cpsr.t.read()) 2 else @as(u32, 4);
 
         const c_psr = self.cpsr.raw;
 
@@ -590,7 +610,7 @@ pub const Arm7tdmi = struct {
         if (self.cpsr.t.read()) {
             if (opcode >> 11 == 0x1E) {
                 // Instruction 1 of a BL Opcode, print in ARM mode
-                const other_half = self.bus.dbgRead(u16, self.r[15]);
+                const other_half = self.bus.debugRead(u16, self.r[15] - 2);
                 const bl_opcode = @as(u32, opcode) << 16 | other_half;
 
                 log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, bl_opcode });
@@ -634,6 +654,59 @@ pub fn checkCond(cpsr: PSR, cond: u4) bool {
     };
 }
 
+const Pipline = struct {
+    const Self = @This();
+    stage: [2]?u32,
+    flushed: bool,
+
+    fn init() Self {
+        return .{
+            .stage = [_]?u32{null} ** 2,
+            .flushed = false,
+        };
+    }
+
+    pub fn flush(self: *Self) void {
+        for (self.stage) |*opcode| opcode.* = null;
+        self.flushed = true;
+
+        // Note: If using this, add
+        // if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
+        // to the end of Arm7tdmi.step
+    }
+
+    pub fn isFull(self: *const Self) bool {
+        return self.stage[0] != null and self.stage[1] != null;
+    }
+
+    pub fn step(self: *Self, cpu: *Arm7tdmi, comptime T: type) ?u32 {
+        comptime std.debug.assert(T == u32 or T == u16);
+
+        // FIXME: https://github.com/ziglang/zig/issues/12642
+        const opcode = self.stage[0..1][0];
+
+        self.stage[0] = self.stage[1];
+        self.stage[1] = cpu.bus.read(T, cpu.r[15]);
+
+        return opcode;
+    }
+
+    pub fn reload(self: *Self, comptime T: type, cpu: *Arm7tdmi) void {
+        comptime std.debug.assert(T == u32 or T == u16);
+
+        // Sometimes, the pipeline can be reloaded twice in the same instruction
+        // This can happen if:
+        // 1. R15 is written to
+        // 2. The CPSR is written to (and T changes), so R15 is written to again
+
+        self.stage[0] = cpu.bus.read(T, cpu.r[15]);
+        self.stage[1] = cpu.bus.read(T, cpu.r[15] + if (T == u32) 4 else @as(u32, 2));
+
+        cpu.r[15] += if (T == u32) 8 else @as(u32, 4);
+        self.flushed = true;
+    }
+};
+
 pub const PSR = extern union {
     mode: Bitfield(u32, 0, 5),
     t: Bit(u32, 5),

src/core/cpu/arm/block_data_transfer.zig

@@ -55,8 +55,10 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
 
                 if (L) {
                     cpu.r[15] = bus.read(u32, und_addr);
+                    cpu.pipe.reload(u32, cpu);
                 } else {
-                    bus.write(u32, und_addr, cpu.r[15] + 8);
+                    // FIXME: Should r15 on write be +12 ahead?
+                    bus.write(u32, und_addr, cpu.r[15] + 4);
                 }
 
                 cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
@@ -86,17 +88,23 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
                     cpu.setUserModeRegister(i, bus.read(u32, address));
                 } else {
                     const value = bus.read(u32, address);
-                    cpu.r[i] = if (i == 0xF) value & 0xFFFF_FFFC else value;
-                    if (S and i == 0xF) cpu.setCpsr(cpu.spsr.raw);
+
+                    cpu.r[i] = value;
+                    if (i == 0xF) {
+                        cpu.r[i] &= ~@as(u32, 3); // Align r15
+                        cpu.pipe.reload(u32, cpu);
+
+                        if (S) cpu.setCpsr(cpu.spsr.raw);
+                    }
                 }
             } else {
                 if (S) {
                     // Always Transfer User mode Registers
                     // This happens regardless if r15 is in the list
                     const value = cpu.getUserModeRegister(i);
-                    bus.write(u32, address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
+                    bus.write(u32, address, value + if (i == 0xF) 4 else @as(u32, 0)); // PC is already 8 ahead to make 12
                 } else {
-                    bus.write(u32, address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
+                    bus.write(u32, address, cpu.r[i] + if (i == 0xF) 4 else @as(u32, 0));
                 }
             }
         }

src/core/cpu/arm/branch.zig

@@ -9,14 +9,20 @@ const sext = @import("../../util.zig").sext;
 pub fn branch(comptime L: bool) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
-            if (L) cpu.r[14] = cpu.r[15];
-            cpu.r[15] = cpu.fakePC() +% (sext(u32, u24, opcode) << 2);
+            if (L) cpu.r[14] = cpu.r[15] - 4;
+
+            cpu.r[15] +%= sext(u32, u24, opcode) << 2;
+            cpu.pipe.reload(u32, cpu);
         }
     }.inner;
 }
 
 pub fn branchAndExchange(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
     const rn = opcode & 0xF;
-    cpu.cpsr.t.write(cpu.r[rn] & 1 == 1);
-    cpu.r[15] = cpu.r[rn] & 0xFFFF_FFFE;
+
+    const thumb = cpu.r[rn] & 1 == 1;
+    cpu.r[15] = cpu.r[rn] & if (thumb) ~@as(u32, 1) else ~@as(u32, 3);
+
+    cpu.cpsr.t.write(thumb);
+    if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
 }

src/core/cpu/arm/data_processing.zig

@@ -5,7 +5,7 @@ const InstrFn = @import("../../cpu.zig").arm.InstrFn;
 const rotateRight = @import("../barrel_shifter.zig").rotateRight;
 const execute = @import("../barrel_shifter.zig").execute;
 
-pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
+pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
             const rd = @truncate(u4, opcode >> 12 & 0xF);
@@ -13,124 +13,276 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
             const old_carry = @boolToInt(cpu.cpsr.c.read());
 
             // If certain conditions are met, PC is 12 ahead instead of 8
+            // TODO: Why these conditions?
             if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
+            const op1 = cpu.r[rn];
 
-            const op1 = if (rn == 0xF) cpu.fakePC() else cpu.r[rn];
-
-            var op2: u32 = undefined;
-            if (I) {
-                const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
-                op2 = rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount);
-            } else {
-                op2 = execute(S, cpu, opcode);
-            }
+            const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
+            const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
 
             // Undo special condition from above
             if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
 
-            switch (instrKind) {
-                0x0 => {
-                    // AND
-                    const result = op1 & op2;
-                    cpu.r[rd] = result;
-                    setArmLogicOpFlags(S, cpu, rd, result);
-                },
-                0x1 => {
-                    // EOR
-                    const result = op1 ^ op2;
-                    cpu.r[rd] = result;
-                    setArmLogicOpFlags(S, cpu, rd, result);
-                },
-                0x2 => {
-                    // SUB
-                    cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
-                },
-                0x3 => {
-                    // RSB
-                    cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
-                },
-                0x4 => {
-                    // ADD
-                    cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
-                },
-                0x5 => {
-                    // ADC
-                    cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
-                },
-                0x6 => {
-                    // SBC
-                    cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
-                },
-                0x7 => {
-                    // RSC
-                    cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
-                },
+            var result: u32 = undefined;
+            var didOverflow: bool = undefined;
+
+            // Perform Data Processing Logic
+            switch (kind) {
+                0x0 => result = op1 & op2, // AND
+                0x1 => result = op1 ^ op2, // EOR
+                0x2 => result = op1 -% op2, // SUB
+                0x3 => result = op2 -% op1, // RSB
+                0x4 => result = newAdd(&didOverflow, op1, op2), // ADD
+                0x5 => result = newAdc(&didOverflow, op1, op2, old_carry), // ADC
+                0x6 => result = newSbc(op1, op2, old_carry), // SBC
+                0x7 => result = newSbc(op2, op1, old_carry), // RSC
                 0x8 => {
                     // TST
-                    if (rd == 0xF) {
-                        undefinedTestBehaviour(cpu);
-                        return;
-                    }
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
 
-                    const result = op1 & op2;
-                    setTestOpFlags(S, cpu, opcode, result);
+                    result = op1 & op2;
                 },
                 0x9 => {
                     // TEQ
-                    if (rd == 0xF) {
-                        undefinedTestBehaviour(cpu);
-                        return;
-                    }
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
 
-                    const result = op1 ^ op2;
-                    setTestOpFlags(S, cpu, opcode, result);
+                    result = op1 ^ op2;
                 },
                 0xA => {
                     // CMP
-                    if (rd == 0xF) {
-                        undefinedTestBehaviour(cpu);
-                        return;
-                    }
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
 
-                    cmp(cpu, op1, op2);
+                    result = op1 -% op2;
                 },
                 0xB => {
                     // CMN
-                    if (rd == 0xF) {
-                        undefinedTestBehaviour(cpu);
-                        return;
-                    }
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
 
-                    cmn(cpu, op1, op2);
+                    didOverflow = @addWithOverflow(u32, op1, op2, &result);
                 },
-                0xC => {
-                    // ORR
-                    const result = op1 | op2;
+                0xC => result = op1 | op2, // ORR
+                0xD => result = op2, // MOV
+                0xE => result = op1 & ~op2, // BIC
+                0xF => result = ~op2, // MVN
+            }
+
+            // Write to Destination Register
+            switch (kind) {
+                0x8, 0x9, 0xA, 0xB => {}, // Test Operations
+                else => {
                     cpu.r[rd] = result;
-                    setArmLogicOpFlags(S, cpu, rd, result);
+                    if (rd == 0xF) cpu.pipe.reload(u32, cpu);
                 },
-                0xD => {
-                    // MOV
-                    cpu.r[rd] = op2;
-                    setArmLogicOpFlags(S, cpu, rd, op2);
+            }
+
+            // Write Flags
+            switch (kind) {
+                0x0, 0x1, 0xC, 0xD, 0xE, 0xF => {
+                    // Logic Operation Flags
+                    if (S) {
+                        if (rd == 0xF) {
+                            cpu.setCpsr(cpu.spsr.raw);
+                        } else {
+                            cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                            cpu.cpsr.z.write(result == 0);
+                            // C set by Barrel Shifter, V is unaffected
+                        }
+                    }
                 },
-                0xE => {
-                    // BIC
-                    const result = op1 & ~op2;
-                    cpu.r[rd] = result;
-                    setArmLogicOpFlags(S, cpu, rd, result);
+                0x2, 0x3 => {
+                    // SUB, RSB Flags
+                    if (S) {
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                        cpu.cpsr.z.write(result == 0);
+
+                        if (kind == 0x2) {
+                            // SUB specific
+                            cpu.cpsr.c.write(op2 <= op1);
+                            cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                        } else {
+                            // RSB Specific
+                            cpu.cpsr.c.write(op1 <= op2);
+                            cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
+                        }
+
+                        if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
+                    }
                 },
-                0xF => {
-                    // MVN
-                    const result = ~op2;
-                    cpu.r[rd] = result;
-                    setArmLogicOpFlags(S, cpu, rd, result);
+                0x4, 0x5 => {
+                    // ADD, ADC Flags
+                    if (S) {
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                        cpu.cpsr.z.write(result == 0);
+                        cpu.cpsr.c.write(didOverflow);
+                        cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+
+                        if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
+                    }
+                },
+                0x6, 0x7 => {
+                    // SBC, RSC Flags
+                    if (S) {
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                        cpu.cpsr.z.write(result == 0);
+
+                        if (kind == 0x6) {
+                            // SBC specific
+                            const subtrahend = @as(u64, op2) -% old_carry +% 1;
+                            cpu.cpsr.c.write(subtrahend <= op1);
+                            cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                        } else {
+                            // RSC Specific
+                            const subtrahend = @as(u64, op1) -% old_carry +% 1;
+                            cpu.cpsr.c.write(subtrahend <= op2);
+                            cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
+                        }
+
+                        if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
+                    }
+                },
+                0x8, 0x9, 0xA, 0xB => {
+                    // Test Operation Flags
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+
+                    if (kind == 0xA) {
+                        // CMP specific
+                        cpu.cpsr.c.write(op2 <= op1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                    } else if (kind == 0xB) {
+                        // CMN specific
+                        cpu.cpsr.c.write(didOverflow);
+                        cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+                    } else {
+                        // TEST, TEQ specific
+                        // Barrel Shifter should always calc CPSR C in TST
+                        if (!S) _ = execute(true, cpu, opcode);
+                    }
                 },
             }
         }
     }.inner;
 }
 
+// pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
+//     return struct {
+//         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+//             const rd = @truncate(u4, opcode >> 12 & 0xF);
+//             const rn = opcode >> 16 & 0xF;
+//             const old_carry = @boolToInt(cpu.cpsr.c.read());
+
+//             // If certain conditions are met, PC is 12 ahead instead of 8
+//             // TODO: What are these conditions? I can't remember
+//             if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
+//             const op1 = cpu.r[rn];
+
+//             const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
+//             const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
+
+//             // Undo special condition from above
+//             if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
+
+//             switch (instrKind) {
+//                 0x0 => {
+//                     // AND
+//                     const result = op1 & op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//                 0x1 => {
+//                     // EOR
+//                     const result = op1 ^ op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//                 0x2 => {
+//                     // SUB
+//                     cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
+//                 },
+//                 0x3 => {
+//                     // RSB
+//                     cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
+//                 },
+//                 0x4 => {
+//                     // ADD
+//                     cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
+//                 },
+//                 0x5 => {
+//                     // ADC
+//                     cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
+//                 },
+//                 0x6 => {
+//                     // SBC
+//                     cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
+//                 },
+//                 0x7 => {
+//                     // RSC
+//                     cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
+//                 },
+//                 0x8 => {
+//                     // TST
+//                     if (rd == 0xF)
+//                         return undefinedTestBehaviour(cpu);
+
+//                     const result = op1 & op2;
+//                     setTestOpFlags(S, cpu, opcode, result);
+//                 },
+//                 0x9 => {
+//                     // TEQ
+//                     if (rd == 0xF)
+//                         return undefinedTestBehaviour(cpu);
+
+//                     const result = op1 ^ op2;
+//                     setTestOpFlags(S, cpu, opcode, result);
+//                 },
+//                 0xA => {
+//                     // CMP
+//                     if (rd == 0xF)
+//                         return undefinedTestBehaviour(cpu);
+
+//                     cmp(cpu, op1, op2);
+//                 },
+//                 0xB => {
+//                     // CMN
+//                     if (rd == 0xF)
+//                         return undefinedTestBehaviour(cpu);
+
+//                     cmn(cpu, op1, op2);
+//                 },
+//                 0xC => {
+//                     // ORR
+//                     const result = op1 | op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//                 0xD => {
+//                     // MOV
+//                     cpu.r[rd] = op2;
+//                     setArmLogicOpFlags(S, cpu, rd, op2);
+//                 },
+//                 0xE => {
+//                     // BIC
+//                     const result = op1 & ~op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//                 0xF => {
+//                     // MVN
+//                     const result = ~op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//             }
+
+//             if (rd == 0xF) cpu.pipe.reload(u32, cpu);
+//         }
+//     }.inner;
+// }
+
 fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
     var result: u32 = undefined;
     if (S and rd == 0xF) {
@@ -143,6 +295,14 @@ fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_c
     return result;
 }
 
+fn newSbc(left: u32, right: u32, old_carry: u1) u32 {
+    // TODO: Make your own version (thanks peach.bot)
+    const subtrahend = @as(u64, right) -% old_carry +% 1;
+    const ret = @truncate(u32, left -% subtrahend);
+
+    return ret;
+}
+
 pub fn sbc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
     // TODO: Make your own version (thanks peach.bot)
     const subtrahend = @as(u64, right) -% old_carry +% 1;
@@ -195,6 +355,12 @@ fn armAdd(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
     return result;
 }
 
+fn newAdd(didOverflow: *bool, left: u32, right: u32) u32 {
+    var ret: u32 = undefined;
+    didOverflow.* = @addWithOverflow(u32, left, right, &ret);
+    return ret;
+}
+
 pub fn add(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
     var result: u32 = undefined;
     const didOverflow = @addWithOverflow(u32, left, right, &result);
@@ -221,6 +387,15 @@ fn armAdc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_c
     return result;
 }
 
+fn newAdc(didOverflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
+    var ret: u32 = undefined;
+    const did = @addWithOverflow(u32, left, right, &ret);
+    const overflow = @addWithOverflow(u32, ret, old_carry, &ret);
+
+    didOverflow.* = did or overflow;
+    return ret;
+}
+
 pub fn adc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
     var result: u32 = undefined;
     const did = @addWithOverflow(u32, left, right, &result);
@@ -280,5 +455,5 @@ fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) vo
 
 fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
     @setCold(true);
-    cpu.setCpsr(cpu.spsr.raw);
+    cpu.setCpsrNoFlush(cpu.spsr.raw);
 }

src/core/cpu/arm/half_signed_data_transfer.zig

@@ -15,20 +15,8 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
             const rm = opcode & 0xF;
             const imm_offset_high = opcode >> 8 & 0xF;
 
-            var base: u32 = undefined;
-            if (rn == 0xF) {
-                base = cpu.fakePC();
-                if (!L) base += 4;
-            } else {
-                base = cpu.r[rn];
-            }
-
-            var offset: u32 = undefined;
-            if (I) {
-                offset = imm_offset_high << 4 | rm;
-            } else {
-                offset = cpu.r[rm];
-            }
+            const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
+            const offset = if (I) imm_offset_high << 4 | rm else cpu.r[rm];
 
             const modified_base = if (U) base +% offset else base -% offset;
             var address = if (P) modified_base else base;

src/core/cpu/arm/single_data_transfer.zig

@@ -14,13 +14,8 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
             const rn = opcode >> 16 & 0xF;
             const rd = opcode >> 12 & 0xF;
 
-            var base: u32 = undefined;
-            if (rn == 0xF) {
-                base = cpu.fakePC();
-                if (!L) base += 4; // Offset of 12
-            } else {
-                base = cpu.r[rn];
-            }
+            // rn is r15 and L is not set, the PC is 12 ahead
+            const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
 
             const offset = if (I) shifter.immShift(false, cpu, opcode) else opcode & 0xFFF;
 
@@ -40,18 +35,26 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
             } else {
                 if (B) {
                     // STRB
-                    const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
+                    const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0); // PC is 12 ahead
                     bus.write(u8, address, @truncate(u8, value));
                 } else {
                     // STR
-                    const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
+                    const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0);
                     bus.write(u32, address, value);
                 }
             }
 
             address = modified_base;
-            if (W and P or !P) cpu.r[rn] = address;
-            if (L) cpu.r[rd] = result; // This emulates the LDR rd == rn behaviour
+            if (W and P or !P) {
+                cpu.r[rn] = address;
+                if (rn == 0xF) cpu.pipe.reload(u32, cpu);
+            }
+
+            if (L) {
+                // This emulates the LDR rd == rn behaviour
+                cpu.r[rd] = result;
+                if (rd == 0xF) cpu.pipe.reload(u32, cpu);
+            }
         }
     }.inner;
 }

src/core/cpu/arm/software_interrupt.zig

@@ -6,7 +6,7 @@ pub fn armSoftwareInterrupt() InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, _: u32) void {
             // Copy Values from Current Mode
-            const r15 = cpu.r[15];
+            const ret_addr = cpu.r[15] - 4;
             const cpsr = cpu.cpsr.raw;
 
             // Switch Mode
@@ -14,9 +14,10 @@ pub fn armSoftwareInterrupt() InstrFn {
             cpu.cpsr.t.write(false); // Force ARM Mode
             cpu.cpsr.i.write(true); // Disable normal interrupts
 
-            cpu.r[14] = r15; // Resume Execution
+            cpu.r[14] = ret_addr; // Resume Execution
             cpu.spsr.raw = cpsr; // Previous mode CPSR
             cpu.r[15] = 0x0000_0008;
+            cpu.pipe.reload(u32, cpu);
         }
     }.inner;
 }

src/core/cpu/barrel_shifter.zig

@@ -18,11 +18,9 @@ pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
 
 fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
     const rs_idx = opcode >> 8 & 0xF;
+    const rm = cpu.r[opcode & 0xF];
     const rs = @truncate(u8, cpu.r[rs_idx]);
 
-    const rm_idx = opcode & 0xF;
-    const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx];
-
     return switch (@truncate(u2, opcode >> 5)) {
         0b00 => logicalLeft(S, &cpu.cpsr, rm, rs),
         0b01 => logicalRight(S, &cpu.cpsr, rm, rs),
@@ -33,9 +31,7 @@ fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
 
 pub fn immShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
     const amount = @truncate(u8, opcode >> 7 & 0x1F);
-
-    const rm_idx = opcode & 0xF;
-    const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx];
+    const rm = cpu.r[opcode & 0xF];
 
     var result: u32 = undefined;
     if (amount == 0) {

src/core/cpu/thumb/block_data_transfer.zig

@@ -33,7 +33,8 @@ pub fn fmt14(comptime L: bool, comptime R: bool) InstrFn {
             if (R) {
                 if (L) {
                     const value = bus.read(u32, address);
-                    cpu.r[15] = value & 0xFFFF_FFFE;
+                    cpu.r[15] = value & ~@as(u32, 1);
+                    cpu.pipe.reload(u16, cpu);
                 } else {
                     bus.write(u32, address, cpu.r[14]);
                 }
@@ -52,7 +53,13 @@ pub fn fmt15(comptime L: bool, comptime rb: u3) InstrFn {
             const end_address = cpu.r[rb] + 4 * countRlist(opcode);
 
             if (opcode & 0xFF == 0) {
-                if (L) cpu.r[15] = bus.read(u32, address) else bus.write(u32, address, cpu.r[15] + 4);
+                if (L) {
+                    cpu.r[15] = bus.read(u32, address);
+                    cpu.pipe.reload(u16, cpu);
+                } else {
+                    bus.write(u32, address, cpu.r[15] + 2);
+                }
+
                 cpu.r[rb] += 0x40;
                 return;
             }

src/core/cpu/thumb/branch.zig

@@ -9,16 +9,13 @@ pub fn fmt16(comptime cond: u4) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
             // B
-            const offset = sext(u32, u8, opcode & 0xFF) << 1;
+            if (cond == 0xE or cond == 0xF)
+                cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond});
 
-            const should_execute = switch (cond) {
-                0xE, 0xF => cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond}),
-                else => checkCond(cpu.cpsr, cond),
-            };
+            if (!checkCond(cpu.cpsr, cond)) return;
 
-            if (should_execute) {
-                cpu.r[15] = (cpu.r[15] + 2) +% offset;
-            }
+            cpu.r[15] +%= sext(u32, u8, opcode & 0xFF) << 1;
+            cpu.pipe.reload(u16, cpu);
         }
     }.inner;
 }
@@ -27,8 +24,8 @@ pub fn fmt18() InstrFn {
     return struct {
         // B but conditional
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
-            const offset = sext(u32, u11, opcode & 0x7FF) << 1;
-            cpu.r[15] = (cpu.r[15] + 2) +% offset;
+            cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
+            cpu.pipe.reload(u16, cpu);
         }
     }.inner;
 }
@@ -41,13 +38,16 @@ pub fn fmt19(comptime is_low: bool) InstrFn {
 
             if (is_low) {
                 // Instruction 2
-                const old_pc = cpu.r[15];
+                const next_opcode = cpu.r[15] - 2;
 
                 cpu.r[15] = cpu.r[14] +% (offset << 1);
-                cpu.r[14] = old_pc | 1;
+                cpu.r[14] = next_opcode | 1;
+
+                cpu.pipe.reload(u16, cpu);
             } else {
                 // Instruction 1
-                cpu.r[14] = (cpu.r[15] + 2) +% (sext(u32, u11, offset) << 12);
+                const lr_offset = sext(u32, u11, offset) << 12;
+                cpu.r[14] = (cpu.r[15] +% lr_offset) & ~@as(u32, 1);
             }
         }
     }.inner;

src/core/cpu/thumb/data_processing.zig

@@ -10,8 +10,6 @@ const sub = @import("../arm/data_processing.zig").sub;
 const cmp = @import("../arm/data_processing.zig").cmp;
 const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
 
-const log = std.log.scoped(.Thumb1);
-
 pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
@@ -58,29 +56,38 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
 pub fn fmt5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
-            const src_idx = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
-            const dst_idx = @as(u4, h1) << 3 | (opcode & 0x7);
+            const rs = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
+            const rd = @as(u4, h1) << 3 | (opcode & 0x7);
 
-            const src = if (src_idx == 0xF) (cpu.r[src_idx] + 2) & 0xFFFF_FFFE else cpu.r[src_idx];
-            const dst = if (dst_idx == 0xF) (cpu.r[dst_idx] + 2) & 0xFFFF_FFFE else cpu.r[dst_idx];
+            const rs_value = if (rs == 0xF) cpu.r[rs] & ~@as(u32, 1) else cpu.r[rs];
+            const rd_value = if (rd == 0xF) cpu.r[rd] & ~@as(u32, 1) else cpu.r[rd];
 
             switch (op) {
                 0b00 => {
                     // ADD
-                    const sum = add(false, cpu, dst, src);
-                    cpu.r[dst_idx] = if (dst_idx == 0xF) sum & 0xFFFF_FFFE else sum;
+                    const sum = add(false, cpu, rd_value, rs_value);
+                    cpu.r[rd] = if (rd == 0xF) sum & ~@as(u32, 1) else sum;
                 },
-                0b01 => cmp(cpu, dst, src), // CMP
+                0b01 => cmp(cpu, rd_value, rs_value), // CMP
                 0b10 => {
                     // MOV
-                    cpu.r[dst_idx] = if (dst_idx == 0xF) src & 0xFFFF_FFFE else src;
+                    cpu.r[rd] = if (rd == 0xF) rs_value & ~@as(u32, 1) else rs_value;
                 },
                 0b11 => {
                     // BX
-                    cpu.cpsr.t.write(src & 1 == 1);
-                    cpu.r[15] = src & 0xFFFF_FFFE;
+                    const thumb = rs_value & 1 == 1;
+                    cpu.r[15] = rs_value & ~@as(u32, 1);
+
+                    cpu.cpsr.t.write(thumb);
+                    if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
+
+                    // TODO: We shouldn't need to worry about the if statement
+                    // below, because in BX, rd SBZ (and H1 is guaranteed to be 0)
+                    return;
                 },
             }
+
+            if (rd == 0xF) cpu.pipe.reload(u16, cpu);
         }
     }.inner;
 }
@@ -133,10 +140,9 @@ pub fn fmt12(comptime isSP: bool, comptime rd: u3) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
             // ADD
-            const left = if (isSP) cpu.r[13] else (cpu.r[15] + 2) & 0xFFFF_FFFD;
+            const left = if (isSP) cpu.r[13] else cpu.r[15] & ~@as(u32, 2);
             const right = (opcode & 0xFF) << 2;
-            const result = left + right;
-            cpu.r[rd] = result;
+            cpu.r[rd] = left + right;
         }
     }.inner;
 }

src/core/cpu/thumb/data_transfer.zig

@@ -11,7 +11,9 @@ pub fn fmt6(comptime rd: u3) InstrFn {
         fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
             // LDR
             const offset = (opcode & 0xFF) << 2;
-            cpu.r[rd] = bus.read(u32, (cpu.r[15] + 2 & 0xFFFF_FFFD) + offset);
+
+            // Bit 1 of the PC intentionally ignored
+            cpu.r[rd] = bus.read(u32, (cpu.r[15] & ~@as(u32, 2)) + offset);
         }
     }.inner;
 }

src/core/cpu/thumb/software_interrupt.zig

@@ -6,7 +6,7 @@ pub fn fmt17() InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, _: u16) void {
             // Copy Values from Current Mode
-            const r15 = cpu.r[15];
+            const ret_addr = cpu.r[15] - 2;
             const cpsr = cpu.cpsr.raw;
 
             // Switch Mode
@@ -14,9 +14,10 @@ pub fn fmt17() InstrFn {
             cpu.cpsr.t.write(false); // Force ARM Mode
             cpu.cpsr.i.write(true); // Disable normal interrupts
 
-            cpu.r[14] = r15; // Resume Execution
+            cpu.r[14] = ret_addr; // Resume Execution
             cpu.spsr.raw = cpsr; // Previous mode CPSR
             cpu.r[15] = 0x0000_0008;
+            cpu.pipe.reload(u32, cpu);
         }
     }.inner;
 }

src/core/ppu.zig

@@ -41,28 +41,25 @@ pub const Ppu = struct {
     oam: Oam,
     sched: *Scheduler,
     framebuf: FrameBuffer,
-    alloc: Allocator,
+    allocator: Allocator,
 
-    scanline_sprites: [128]?Sprite,
+    scanline_sprites: *[128]?Sprite,
     scanline: Scanline,
 
-    pub fn init(alloc: Allocator, sched: *Scheduler) !Self {
+    pub fn init(allocator: Allocator, sched: *Scheduler) !Self {
         // Queue first Hblank
         sched.push(.Draw, 240 * 4);
 
-        const framebufs = try alloc.alloc(u8, (framebuf_pitch * height) * 2);
-        std.mem.set(u8, framebufs, 0);
-
-        const scanline_buf = try alloc.alloc(?u16, width * 2);
-        std.mem.set(?u16, scanline_buf, null);
+        const sprites = try allocator.create([128]?Sprite);
+        sprites.* = [_]?Sprite{null} ** 128;
 
         return Self{
-            .vram = try Vram.init(alloc),
-            .palette = try Palette.init(alloc),
-            .oam = try Oam.init(alloc),
+            .vram = try Vram.init(allocator),
+            .palette = try Palette.init(allocator),
+            .oam = try Oam.init(allocator),
             .sched = sched,
-            .framebuf = FrameBuffer.init(framebufs),
-            .alloc = alloc,
+            .framebuf = try FrameBuffer.init(allocator),
+            .allocator = allocator,
 
             // Registers
             .win = Window.init(),
@@ -75,17 +72,19 @@ pub const Ppu = struct {
             .bldalpha = .{ .raw = 0x0000 },
             .bldy = .{ .raw = 0x0000 },
 
-            .scanline = Scanline.init(scanline_buf),
-            .scanline_sprites = [_]?Sprite{null} ** 128,
+            .scanline = try Scanline.init(allocator),
+            .scanline_sprites = sprites,
         };
     }
 
-    pub fn deinit(self: Self) void {
-        self.framebuf.deinit(self.alloc);
-        self.scanline.deinit(self.alloc);
+    pub fn deinit(self: *Self) void {
+        self.allocator.destroy(self.scanline_sprites);
+        self.framebuf.deinit();
+        self.scanline.deinit();
         self.vram.deinit();
         self.palette.deinit();
         self.oam.deinit();
+        self.* = undefined;
     }
 
     pub fn setBgOffsets(self: *Self, comptime n: u2, word: u32) void {
@@ -399,7 +398,7 @@ pub const Ppu = struct {
                 // Reset Current Scanline Pixel Buffer and list of fetched sprites
                 // in prep for next scanline
                 self.scanline.reset();
-                std.mem.set(?Sprite, &self.scanline_sprites, null);
+                std.mem.set(?Sprite, self.scanline_sprites, null);
             },
             0x1 => {
                 const fb_base = framebuf_pitch * @as(usize, scanline);
@@ -426,7 +425,7 @@ pub const Ppu = struct {
                 // Reset Current Scanline Pixel Buffer and list of fetched sprites
                 // in prep for next scanline
                 self.scanline.reset();
-                std.mem.set(?Sprite, &self.scanline_sprites, null);
+                std.mem.set(?Sprite, self.scanline_sprites, null);
             },
             0x2 => {
                 const fb_base = framebuf_pitch * @as(usize, scanline);
@@ -452,7 +451,7 @@ pub const Ppu = struct {
                 // Reset Current Scanline Pixel Buffer and list of fetched sprites
                 // in prep for next scanline
                 self.scanline.reset();
-                std.mem.set(?Sprite, &self.scanline_sprites, null);
+                std.mem.set(?Sprite, self.scanline_sprites, null);
             },
             0x3 => {
                 const vram_base = width * @sizeOf(u16) * @as(usize, scanline);
@@ -629,20 +628,21 @@ const Palette = struct {
     const Self = @This();
 
     buf: []u8,
-    alloc: Allocator,
+    allocator: Allocator,
 
-    fn init(alloc: Allocator) !Self {
-        const buf = try alloc.alloc(u8, palram_size);
+    fn init(allocator: Allocator) !Self {
+        const buf = try allocator.alloc(u8, palram_size);
         std.mem.set(u8, buf, 0);
 
         return Self{
             .buf = buf,
-            .alloc = alloc,
+            .allocator = allocator,
         };
     }
 
-    fn deinit(self: Self) void {
-        self.alloc.free(self.buf);
+    fn deinit(self: *Self) void {
+        self.allocator.free(self.buf);
+        self.* = undefined;
     }
 
     pub fn read(self: *const Self, comptime T: type, address: usize) T {
@@ -677,20 +677,21 @@ const Vram = struct {
     const Self = @This();
 
     buf: []u8,
-    alloc: Allocator,
+    allocator: Allocator,
 
-    fn init(alloc: Allocator) !Self {
-        const buf = try alloc.alloc(u8, vram_size);
+    fn init(allocator: Allocator) !Self {
+        const buf = try allocator.alloc(u8, vram_size);
         std.mem.set(u8, buf, 0);
 
         return Self{
             .buf = buf,
-            .alloc = alloc,
+            .allocator = allocator,
         };
     }
 
-    fn deinit(self: Self) void {
-        self.alloc.free(self.buf);
+    fn deinit(self: *Self) void {
+        self.allocator.free(self.buf);
+        self.* = undefined;
     }
 
     pub fn read(self: *const Self, comptime T: type, address: usize) T {
@@ -737,20 +738,21 @@ const Oam = struct {
     const Self = @This();
 
     buf: []u8,
-    alloc: Allocator,
+    allocator: Allocator,
 
-    fn init(alloc: Allocator) !Self {
-        const buf = try alloc.alloc(u8, oam_size);
+    fn init(allocator: Allocator) !Self {
+        const buf = try allocator.alloc(u8, oam_size);
         std.mem.set(u8, buf, 0);
 
         return Self{
             .buf = buf,
-            .alloc = alloc,
+            .allocator = allocator,
         };
     }
 
-    fn deinit(self: Self) void {
-        self.alloc.free(self.buf);
+    fn deinit(self: *Self) void {
+        self.allocator.free(self.buf);
+        self.* = undefined;
     }
 
     pub fn read(self: *const Self, comptime T: type, address: usize) T {
@@ -1213,35 +1215,38 @@ fn copyToSpriteBuffer(bldcnt: io.BldCnt, scanline: *Scanline, x: u9, bgr555: u16
 const Scanline = struct {
     const Self = @This();
 
-    buf: [2][]?u16,
-    original: []?u16,
+    layers: [2][]?u16,
+    buf: []?u16,
 
-    fn init(buf: []?u16) Self {
-        std.debug.assert(buf.len == width * 2);
+    allocator: Allocator,
 
-        const top_slice = buf[0..][0..width];
-        const btm_slice = buf[width..][0..width];
+    fn init(allocator: Allocator) !Self {
+        const buf = try allocator.alloc(?u16, width * 2); // Top & Bottom Scanline
+        std.mem.set(?u16, buf, null);
 
         return .{
-            .buf = [_][]?u16{ top_slice, btm_slice },
-            .original = buf,
+            // Top & Bototm Layers
+            .layers = [_][]?u16{ buf[0..][0..width], buf[width..][0..width] },
+            .buf = buf,
+            .allocator = allocator,
         };
     }
 
     fn reset(self: *Self) void {
-        std.mem.set(?u16, self.original, null);
+        std.mem.set(?u16, self.buf, null);
     }
 
-    fn deinit(self: Self, alloc: Allocator) void {
-        alloc.free(self.original);
+    fn deinit(self: *Self) void {
+        self.allocator.free(self.buf);
+        self.* = undefined;
     }
 
     fn top(self: *Self) []?u16 {
-        return self.buf[0];
+        return self.layers[0];
     }
 
     fn btm(self: *Self) []?u16 {
-        return self.buf[1];
+        return self.layers[1];
     }
 };
 
@@ -1249,31 +1254,36 @@ const Scanline = struct {
 const FrameBuffer = struct {
     const Self = @This();
 
-    buf: [2][]u8,
-    original: []u8,
+    layers: [2][]u8,
+    buf: []u8,
     current: u1,
 
+    allocator: Allocator,
+
     // TODO: Rename
     const Device = enum {
         Emulator,
         Renderer,
     };
 
-    pub fn init(bufs: []u8) Self {
-        std.debug.assert(bufs.len == framebuf_pitch * height * 2);
-
-        const front = bufs[0 .. framebuf_pitch * height];
-        const back = bufs[framebuf_pitch * height ..];
+    pub fn init(allocator: Allocator) !Self {
+        const framebuf_len = framebuf_pitch * height;
+        const buf = try allocator.alloc(u8, framebuf_len * 2);
+        std.mem.set(u8, buf, 0);
 
         return .{
-            .buf = [2][]u8{ front, back },
-            .original = bufs,
+            // Front and Back Framebuffers
+            .layers = [_][]u8{ buf[0..][0..framebuf_len], buf[framebuf_len..][0..framebuf_len] },
+            .buf = buf,
             .current = 0,
+
+            .allocator = allocator,
         };
     }
 
-    fn deinit(self: Self, alloc: Allocator) void {
-        alloc.free(self.original);
+    fn deinit(self: *Self) void {
+        self.allocator.free(self.buf);
+        self.* = undefined;
     }
 
     pub fn swap(self: *Self) void {
@@ -1281,6 +1291,6 @@ const FrameBuffer = struct {
     }
 
     pub fn get(self: *Self, comptime dev: Device) []u8 {
-        return self.buf[if (dev == .Emulator) self.current else ~self.current];
+        return self.layers[if (dev == .Emulator) self.current else ~self.current];
     }
 };

src/core/scheduler.zig

@@ -14,15 +14,16 @@ pub const Scheduler = struct {
     tick: u64,
     queue: PriorityQueue(Event, void, lessThan),
 
-    pub fn init(alloc: Allocator) Self {
-        var sched = Self{ .tick = 0, .queue = PriorityQueue(Event, void, lessThan).init(alloc, {}) };
+    pub fn init(allocator: Allocator) Self {
+        var sched = Self{ .tick = 0, .queue = PriorityQueue(Event, void, lessThan).init(allocator, {}) };
         sched.queue.add(.{ .kind = .HeatDeath, .tick = std.math.maxInt(u64) }) catch unreachable;
 
         return sched;
     }
 
-    pub fn deinit(self: Self) void {
+    pub fn deinit(self: *Self) void {
         self.queue.deinit();
+        self.* = undefined;
     }
 
     pub inline fn now(self: *const Self) u64 {

src/core/util.zig

@@ -127,47 +127,48 @@ pub const Logger = struct {
 
     pub fn print(self: *Self, comptime format: []const u8, args: anytype) !void {
         try self.buf.writer().print(format, args);
+        try self.buf.flush(); // FIXME: On panics, whatever is in the buffer isn't written to file
     }
 
-    pub fn mgbaLog(self: *Self, arm7tdmi: *const Arm7tdmi, opcode: u32) void {
+    pub fn mgbaLog(self: *Self, cpu: *const Arm7tdmi, opcode: u32) void {
         const fmt_base = "{X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} cpsr: {X:0>8} | ";
         const thumb_fmt = fmt_base ++ "{X:0>4}:\n";
         const arm_fmt = fmt_base ++ "{X:0>8}:\n";
 
-        if (arm7tdmi.cpsr.t.read()) {
+        if (cpu.cpsr.t.read()) {
             if (opcode >> 11 == 0x1E) {
                 // Instruction 1 of a BL Opcode, print in ARM mode
-                const low = arm7tdmi.bus.dbgRead(u16, arm7tdmi.r[15]);
+                const low = cpu.bus.dbgRead(u16, cpu.r[15]);
                 const bl_opcode = @as(u32, opcode) << 16 | low;
 
-                self.print(arm_fmt, Self.fmtArgs(arm7tdmi, bl_opcode)) catch @panic("failed to write to log file");
+                self.print(arm_fmt, Self.fmtArgs(cpu, bl_opcode)) catch @panic("failed to write to log file");
             } else {
-                self.print(thumb_fmt, Self.fmtArgs(arm7tdmi, opcode)) catch @panic("failed to write to log file");
+                self.print(thumb_fmt, Self.fmtArgs(cpu, opcode)) catch @panic("failed to write to log file");
             }
         } else {
-            self.print(arm_fmt, Self.fmtArgs(arm7tdmi, opcode)) catch @panic("failed to write to log file");
+            self.print(arm_fmt, Self.fmtArgs(cpu, opcode)) catch @panic("failed to write to log file");
         }
     }
 
-    fn fmtArgs(arm7tdmi: *const Arm7tdmi, opcode: u32) FmtArgTuple {
+    fn fmtArgs(cpu: *const Arm7tdmi, opcode: u32) FmtArgTuple {
         return .{
-            arm7tdmi.r[0],
-            arm7tdmi.r[1],
-            arm7tdmi.r[2],
-            arm7tdmi.r[3],
-            arm7tdmi.r[4],
-            arm7tdmi.r[5],
-            arm7tdmi.r[6],
-            arm7tdmi.r[7],
-            arm7tdmi.r[8],
-            arm7tdmi.r[9],
-            arm7tdmi.r[10],
-            arm7tdmi.r[11],
-            arm7tdmi.r[12],
-            arm7tdmi.r[13],
-            arm7tdmi.r[14],
-            arm7tdmi.r[15],
-            arm7tdmi.cpsr.raw,
+            cpu.r[0],
+            cpu.r[1],
+            cpu.r[2],
+            cpu.r[3],
+            cpu.r[4],
+            cpu.r[5],
+            cpu.r[6],
+            cpu.r[7],
+            cpu.r[8],
+            cpu.r[9],
+            cpu.r[10],
+            cpu.r[11],
+            cpu.r[12],
+            cpu.r[13],
+            cpu.r[14],
+            cpu.r[15] - if (cpu.cpsr.t.read()) 2 else @as(u32, 4),
+            cpu.cpsr.raw,
             opcode,
         };
     }

src/main.zig

@@ -14,7 +14,7 @@ const Allocator = std.mem.Allocator;
 const log = std.log.scoped(.CLI);
 const width = @import("core/ppu.zig").width;
 const height = @import("core/ppu.zig").height;
-const arm7tdmi_logging = @import("core/emu.zig").cpu_logging;
+const cpu_logging = @import("core/emu.zig").cpu_logging;
 pub const log_level = if (builtin.mode != .Debug) .info else std.log.default_level;
 
 // TODO: Reimpl Logging
@@ -40,27 +40,25 @@ pub fn main() anyerror!void {
     const paths = try handleArguments(allocator, &result);
     defer if (paths.save) |path| allocator.free(path);
 
+    const log_file: ?std.fs.File = if (cpu_logging) try std.fs.cwd().createFile("zba.log", .{}) else null;
+    defer if (log_file) |file| file.close();
+
     // TODO: Take Emulator Init Code out of main.zig
     var scheduler = Scheduler.init(allocator);
     defer scheduler.deinit();
 
-    var bus = try Bus.init(allocator, &scheduler, paths);
+    var bus: Bus = undefined;
+    var cpu = Arm7tdmi.init(&scheduler, &bus, log_file);
+    if (paths.bios == null) cpu.fastBoot();
+
+    try bus.init(allocator, &scheduler, &cpu, paths);
     defer bus.deinit();
 
-    var arm7tdmi = Arm7tdmi.init(&scheduler, &bus);
-
-    const log_file: ?std.fs.File = if (arm7tdmi_logging) try std.fs.cwd().createFile("zba.log", .{}) else null;
-    defer if (log_file) |file| file.close();
-
-    if (log_file) |file| arm7tdmi.attach(file);
-    bus.attach(&arm7tdmi); // TODO: Shrink Surface (only CPSR and  r15?)
-    if (paths.bios == null) arm7tdmi.fastBoot();
-
     var gui = Gui.init(bus.pak.title, width, height);
     gui.initAudio(&bus.apu);
     defer gui.deinit();
 
-    try gui.run(&arm7tdmi, &scheduler);
+    try gui.run(&cpu, &scheduler);
 }
 
 fn getSavePath(allocator: Allocator) !?[]const u8 {