Compare commits
No commits in common. "f10670d5e3ee0d9f691003cea79ef5db2cf5b4fe" and "0cf052838dc99c76b610112ff874b882eda59c7e" have entirely different histories.
f10670d5e3
...
0cf052838d
17
src/cpu.zig
17
src/cpu.zig
|
@ -7,7 +7,6 @@ const Bit = @import("bitfield").Bit;
|
||||||
const Bitfield = @import("bitfield").Bitfield;
|
const Bitfield = @import("bitfield").Bitfield;
|
||||||
const Scheduler = @import("scheduler.zig").Scheduler;
|
const Scheduler = @import("scheduler.zig").Scheduler;
|
||||||
|
|
||||||
// ARM Instruction Groups
|
|
||||||
const dataProcessing = @import("cpu/arm/data_processing.zig").dataProcessing;
|
const dataProcessing = @import("cpu/arm/data_processing.zig").dataProcessing;
|
||||||
const psrTransfer = @import("cpu/arm/psr_transfer.zig").psrTransfer;
|
const psrTransfer = @import("cpu/arm/psr_transfer.zig").psrTransfer;
|
||||||
const singleDataTransfer = @import("cpu/arm/single_data_transfer.zig").singleDataTransfer;
|
const singleDataTransfer = @import("cpu/arm/single_data_transfer.zig").singleDataTransfer;
|
||||||
|
@ -16,9 +15,6 @@ const blockDataTransfer = @import("cpu/arm/block_data_transfer.zig").blockDataTr
|
||||||
const branch = @import("cpu/arm/branch.zig").branch;
|
const branch = @import("cpu/arm/branch.zig").branch;
|
||||||
const branchAndExchange = @import("cpu/arm/branch.zig").branchAndExchange;
|
const branchAndExchange = @import("cpu/arm/branch.zig").branchAndExchange;
|
||||||
|
|
||||||
// THUMB Instruction Groups
|
|
||||||
const format3 = @import("cpu/thumb/format3.zig").format3;
|
|
||||||
|
|
||||||
pub const ArmInstrFn = fn (*Arm7tdmi, *Bus, u32) void;
|
pub const ArmInstrFn = fn (*Arm7tdmi, *Bus, u32) void;
|
||||||
pub const ThumbInstrFn = fn (*Arm7tdmi, *Bus, u16) void;
|
pub const ThumbInstrFn = fn (*Arm7tdmi, *Bus, u16) void;
|
||||||
const arm_lut: [0x1000]ArmInstrFn = armPopulate();
|
const arm_lut: [0x1000]ArmInstrFn = armPopulate();
|
||||||
|
@ -145,17 +141,12 @@ fn checkCond(cpsr: PSR, cond: u4) bool {
|
||||||
|
|
||||||
fn thumbPopulate() [0x400]ThumbInstrFn {
|
fn thumbPopulate() [0x400]ThumbInstrFn {
|
||||||
return comptime {
|
return comptime {
|
||||||
@setEvalBranchQuota(0xC00);
|
@setEvalBranchQuota(0x800);
|
||||||
var lut = [_]ThumbInstrFn{thumbUndefined} ** 0x400;
|
var lut = [_]ThumbInstrFn{thumbUndefined} ** 0x400;
|
||||||
|
|
||||||
var i: usize = 0;
|
var i: usize = 0;
|
||||||
while (i < lut.len) : (i += 1) {
|
while (i < lut.len) : (i += 1) {
|
||||||
if (i >> 7 & 0x7 == 0b001) {
|
lut[i] = thumbUndefined;
|
||||||
const op = i >> 5 & 0x3;
|
|
||||||
const rd = i >> 2 & 0x7;
|
|
||||||
|
|
||||||
lut[i] = format3(op, rd);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return lut;
|
return lut;
|
||||||
|
@ -254,10 +245,10 @@ const Mode = enum(u5) {
|
||||||
|
|
||||||
fn armUndefined(_: *Arm7tdmi, _: *Bus, opcode: u32) void {
|
fn armUndefined(_: *Arm7tdmi, _: *Bus, opcode: u32) void {
|
||||||
const id = armIdx(opcode);
|
const id = armIdx(opcode);
|
||||||
std.debug.panic("[CPU:ARM] ID: 0x{X:0>3} 0x{X:0>8} is an illegal opcode", .{ id, opcode });
|
std.debug.panic("[CPU] {{0x{X:}}} 0x{X:} is an illegal opcode", .{ id, opcode });
|
||||||
}
|
}
|
||||||
|
|
||||||
fn thumbUndefined(_: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
fn thumbUndefined(_: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||||
const id = thumbIdx(opcode);
|
const id = thumbIdx(opcode);
|
||||||
std.debug.panic("[CPU:THUMB] ID: 0b{b:0>10} 0x{X:0>2} is an illegal opcode", .{ id, opcode });
|
std.debug.panic("[CPU] {{0x{X:}}} 0x{X:} is an illegal opcode", .{ id, opcode });
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue