fix(dma): implement obscure behaviour for DMAs from ROM

src/core/bus/backup.zig

@@ -40,61 +40,18 @@ pub const Backup = struct {
         None,
     };
 
-    pub fn read(self: *const Self, address: usize) u8 {
+    pub fn read(self: *const Self, address: u32) u8 {
-        const addr = address & 0xFFFF;
-
         switch (self.kind) {
-            .Flash => {
+            .Flash, .Flash1M => return self.flash.read(self.buf, address),
-                switch (addr) {
+            .Sram => return self.buf[address & 0x7FFF], // 32K SRAM chip is mirrored
-                    0x0000 => if (self.flash.id_mode) return 0x32, // Panasonic manufacturer ID
-                    0x0001 => if (self.flash.id_mode) return 0x1B, // Panasonic device ID
-                    else => {},
-                }
-
-                return self.flash.read(self.buf, addr);
-            },
-            .Flash1M => {
-                switch (addr) {
-                    0x0000 => if (self.flash.id_mode) return 0x62, // Sanyo manufacturer ID
-                    0x0001 => if (self.flash.id_mode) return 0x13, // Sanyo device ID
-                    else => {},
-                }
-
-                return self.flash.read(self.buf, addr);
-            },
-            .Sram => return self.buf[addr & 0x7FFF], // 32K SRAM chip is mirrored
             .None, .Eeprom => return 0xFF,
         }
     }
 
-    pub fn write(self: *Self, address: usize, byte: u8) void {
+    pub fn write(self: *Self, address: u32, value: u8) void {
-        const addr = address & 0xFFFF;
-
         switch (self.kind) {
-            .Flash, .Flash1M => {
+            .Flash, .Flash1M => self.flash.write(self.buf, address, value),
-                if (self.flash.prep_write) return self.flash.write(self.buf, addr, byte);
+            .Sram => self.buf[address & 0x7FFF] = value,
-                if (self.flash.shouldEraseSector(addr, byte)) return self.flash.erase(self.buf, addr);
-
-                switch (addr) {
-                    0x0000 => if (self.kind == .Flash1M and self.flash.set_bank) {
-                        self.flash.bank = @truncate(u1, byte);
-                    },
-                    0x5555 => {
-                        if (self.flash.state == .Command) {
-                            self.flash.handleCommand(self.buf, byte);
-                        } else if (byte == 0xAA and self.flash.state == .Ready) {
-                            self.flash.state = .Set;
-                        } else if (byte == 0xF0) {
-                            self.flash.state = .Ready;
-                        }
-                    },
-                    0x2AAA => if (byte == 0x55 and self.flash.state == .Set) {
-                        self.flash.state = .Command;
-                    },
-                    else => {},
-                }
-            },
-            .Sram => self.buf[addr & 0x7FFF] = byte,
             .None, .Eeprom => {},
         }
     }
@@ -118,7 +75,7 @@ pub const Backup = struct {
             .kind = kind,
             .title = title,
             .save_path = path,
-            .flash = Flash.create(),
+            .flash = try Flash.create(if (kind == .Flash1M) .Flash1M else .Flash),
             .eeprom = Eeprom.create(allocator),
         };
 

src/core/bus/backup/Flash.zig

@@ -3,42 +3,83 @@ const std = @import("std");
 const Self = @This();
 
 state: State,
+kind: Kind,
+bank: u1,
 
 id_mode: bool,
 set_bank: bool,
 prep_erase: bool,
 prep_write: bool,
 
-bank: u1,
+const Kind = enum { Flash, Flash1M };
+const State = enum { Ready, Set, Command };
 
-const State = enum {
+pub fn read(self: *const Self, buf: []u8, address: u32) u8 {
-    Ready,
+    const addr = address & 0xFFFF;
-    Set,
-    Command,
-};
 
-pub fn read(self: *const Self, buf: []u8, idx: usize) u8 {
+    if (self.kind == .Flash1M) {
-    return buf[self.address() + idx];
+        switch (addr) {
+            0x0000 => if (self.id_mode) return 0x32, // Panasonic manufacturer ID
+            0x0001 => if (self.id_mode) return 0x1B, // Panasonic device ID
+            else => {},
+        }
+    } else {
+        switch (addr) {
+            0x0000 => if (self.id_mode) return 0x62, // Sanyo manufacturer ID
+            0x0001 => if (self.id_mode) return 0x13, // Sanyo device ID
+            else => {},
+        }
     }
 
-pub fn write(self: *Self, buf: []u8, idx: usize, byte: u8) void {
+    return buf[self.baseAddress() + addr];
-    buf[self.address() + idx] = byte;
+}
+
+pub fn write(self: *Self, buf: []u8, address: u32, value: u8) void {
+    const addr = address & 0xFFFF;
+
+    if (self.prep_write) return self._write(buf, addr, value);
+    if (self.shouldEraseSector(addr, value)) return self.erase(buf, addr);
+
+    switch (addr) {
+        0x0000 => if (self.kind == .Flash1M and self.set_bank) {
+            self.bank = @truncate(u1, value);
+        },
+        0x5555 => {
+            if (self.state == .Command) {
+                self.handleCommand(buf, value);
+            } else if (value == 0xAA and self.state == .Ready) {
+                self.state = .Set;
+            } else if (value == 0xF0) {
+                self.state = .Ready;
+            }
+        },
+        0x2AAA => if (value == 0x55 and self.state == .Set) {
+            self.state = .Command;
+        },
+        else => {},
+    }
+}
+
+fn _write(self: *Self, buf: []u8, idx: usize, byte: u8) void {
+    buf[self.baseAddress() + idx] = byte;
     self.prep_write = false;
 }
 
-pub fn create() Self {
+pub fn create(kind: Kind) !Self {
     return .{
         .state = .Ready,
+        .kind = kind,
+        .bank = 0,
+
         .id_mode = false,
         .set_bank = false,
         .prep_erase = false,
         .prep_write = false,
-        .bank = 0,
     };
 }
 
-pub fn handleCommand(self: *Self, buf: []u8, byte: u8) void {
+fn handleCommand(self: *Self, buf: []u8, value: u8) void {
-    switch (byte) {
+    switch (value) {
         0x90 => self.id_mode = true,
         0xF0 => self.id_mode = false,
         0xB0 => self.set_bank = true,
@@ -48,18 +89,18 @@ pub fn handleCommand(self: *Self, buf: []u8, byte: u8) void {
             self.prep_erase = false;
         },
         0xA0 => self.prep_write = true,
-        else => std.debug.panic("Unhandled Flash Command: 0x{X:0>2}", .{byte}),
+        else => std.debug.panic("Unhandled Flash Command: 0x{X:0>2}", .{value}),
     }
 
     self.state = .Ready;
 }
 
-pub fn shouldEraseSector(self: *const Self, addr: usize, byte: u8) bool {
+fn shouldEraseSector(self: *const Self, addr: usize, byte: u8) bool {
     return self.state == .Command and self.prep_erase and byte == 0x30 and addr & 0xFFF == 0x000;
 }
 
-pub fn erase(self: *Self, buf: []u8, sector: usize) void {
+fn erase(self: *Self, buf: []u8, sector: usize) void {
-    const start = self.address() + (sector & 0xF000);
+    const start = self.baseAddress() + (sector & 0xF000);
 
     std.mem.set(u8, buf[start..][0..0x1000], 0xFF);
     self.prep_erase = false;
@@ -67,6 +108,6 @@ pub fn erase(self: *Self, buf: []u8, sector: usize) void {
 }
 
 /// Base Address
-inline fn address(self: *const Self) usize {
+inline fn baseAddress(self: *const Self) usize {
     return if (self.bank == 1) 0x10000 else @as(usize, 0);
 }

src/core/bus/dma.zig

@@ -256,11 +256,16 @@ fn DmaController(comptime id: u2) type {
                 cpu.bus.write(u16, dad_addr, @truncate(u16, rotr(u32, self.data_latch, 8 * (dad_addr & 3))));
             }
 
-            switch (sad_adj) {
+            switch (@truncate(u8, sad_addr >> 24)) {
+                // according to fleroviux, DMAs with a source address in ROM misbehave
+                // the resultant behaviour is that the source address will increment despite what DMAXCNT says
+                0x08...0x0D => self.sad_latch +%= offset, // obscure behaviour
+                else => switch (sad_adj) {
                     .Increment => self.sad_latch +%= offset,
                     .Decrement => self.sad_latch -%= offset,
                     .IncrementReload => log.err("{} is a prohibited adjustment on SAD", .{sad_adj}),
                     .Fixed => {},
+                },
             }
 
             switch (dad_adj) {

src/util.zig

@@ -145,7 +145,7 @@ pub const Logger = struct {
         if (cpu.cpsr.t.read()) {
             if (opcode >> 11 == 0x1E) {
                 // Instruction 1 of a BL Opcode, print in ARM mode
-                const low = cpu.bus.dbgRead(u16, cpu.r[15]);
+                const low = cpu.bus.dbgRead(u16, cpu.r[15] - 2);
                 const bl_opcode = @as(u32, opcode) << 16 | low;
 
                 self.print(arm_fmt, Self.fmtArgs(cpu, bl_opcode)) catch @panic("failed to write to log file");